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EZ-USB FX2 Technical Reference Manual

Page 4-8 EZ-USB FX2 Technical Reference Manual v2.1

4.3.2 Interrupt Sampling

The internal timers and serial ports generate interrupts by setting the interrupt flag bits shown in

Table 4-9. These interrupts are sampled once per instruction cycle (i.e., once every 4 CLKOUT

cycles).

INT0 and INT1 are both active low and can be programmed to be either edge-sensitive or level-

sensitive, through the IT0 and IT1 bits in the TCON SFR. When ITx = 0, INTx is level-sensitive and

the FX2 sets the IEx flag when the INTx

pin is sampled low. When ITx = 1, INTx is edge-sensitive

and the FX2 sets the IEx flag when the INTx

pin is sampled high then low on consecutive samples.

The remaining five interrupts (INT 4-6, USB &

I²C-Compatible Bus interrupts) are edge-sensitive

only. INT6

and INT4 are active high and INT5 is active low.

To ensure that edge-sensitive interrupts are detected, the interrupt pins should be held in each

state for a minimum of one instruction cycle (4 CLKOUT

cycles). Level-sensitive interrupts are not

latched; their pins must remain asserted until the interrupt is serviced.

4.3.3 Interrupt Latency

Interrupt response time depends on the current state of the FX2. The fastest response time is 5

instruction cycles: 1 to detect the interrupt, and 4 to perform the LCALL to the ISR.

The maximum latency is 13 instruction cycles. This 13-cycle latency occurs when the FX2 is cur-

rently executing a RETI instruction followed by a MUL or DIV instruction. The 13 instruction cycles

in this case are: 1 to detect the interrupt, 3 to complete the RETI, 5 to execute the DIV or MUL, and

4 to execute the LCALL to the ISR.

This13-instruction-cycle latency excludes autovector latency for the USB and FIFO/GPIF inter-

rupts (see Sections 4.5 and 4.8). Autovectoring adds a fixed 4 instruction cycles, so the maximum

latency for an autovectored USB or FIFO/GPIF interrupt is 13 + 4 = 17 instruction cycles.

4.4 USB-Specific Interrupts

The FX2 provides 28 USB-specific interrupts. One, “Resume”, has its own dedicated interrupt; the

other 27 share the “USB” interrupt.

4.4.1 Resume Interrupt

After the FX2 has entered its idle state, it responds to an external signal on its WAKEUP/WU2 pins

or resumption of USB bus activity by restarting its oscillator and resuming firmware execution.

Chapter 6, "Power Management"

describes suspend/resume signaling in detail, and presents an

example which uses the Wakeup Interrupt.

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Cypress Semiconductor FX2LP Información técnica Pagina 98