Cypress Semiconductor FX2LP Información técnica descargar pdf (Pagina 150)

EZ-USB FX2 Technical Reference Manual

Page 8-14 EZ-USB FX2 Technical Reference Manual v2.1

8.6.3.1 IBNIE, IBNIRQ, NAKIE, NAKIRQ

These registers contain the interrupt-enable and interrupt-request bits for two endpoint conditions,

IN-BULK-NAK and PING.

IN-BULK-NAK (IBN)

When the host requests an IN packet from an FX2 BULK endpoint, the endpoint NAKs (returns the

NAK PID) until the endpoint buffer is filled with data and armed for transfer, at which point the FX2

answers the IN request with data.

Until the endpoint is armed, a flood of IN-NAKs can tie up bus bandwidth. Therefore, if the IN end-

points aren’t always kept full and armed, it may be useful to know when the host is “knocking at

the door”, requesting IN data.

The IN-BULK-NAK (IBN) interrupt provides this notification. The IBN interrupt fires whenever a

BULK endpoint NAKs an IN request. The IBNIE/IBNIRQ registers contain individual enable and

request bits per endpoint, and the NAKIE/NAKIRQ registers each contain a single bit, IBN, that is

the OR’d combination of the individual bits in IBNIE/IBNIRQ, respectively.

Firmware enables an interrupt by setting the enable bit high, and clears an interrupt request bit by

writing a 1 to it.

The FX2 interrupt system is described in detail in Chapter 4, "Interrupts."

The IBNIE register contains an individual interrupt-enable bit for each endpoint: EP0, EP1, EP2,

EP4, EP6 and EP8. These bits are valid only if the endpoint is configured as a BULK or INTER-

RUPT endpoint. The IBNIRQ register similarly contains individual interrupt request bits for the 6

endpoints.

The IBN interrupt-service routine should take the following actions, in the order shown:

1. Clear the USB (INT2) interrupt request (by writing 0 to it).

2. Inspect the endpoint bits in IBNIRQ to determine which IN endpoint just NAK’d.

3. Take the required action (set a flag, arm the endpoint, etc.), then clear the individual IBN bit in

IBNIRQ for the serviced endpoint (by writing 1 to it).

4. Repeat steps (2) and (3) for any other endpoints that require IBN service, until all IRQ bits are

cleared.

5. Clear the IBN bit in the NAKIRQ register (by writing 1 to it).

Because the IBN bit represents the OR’d combination of the individual IBN interrupt requests, it

will not “fire” again until all individual IBN interrupt requests have been serviced and cleared.

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Cypress Semiconductor FX2LP Información técnica Pagina 150