Cypress Semiconductor FX2LP Información técnica descargar pdf (Pagina 213)

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Chapter 10. General Programmable Interface (GPIF) Page 10-23

OPCODE Register: This register sets a number of State characteristics.

SGL Bit: has no effect in a Single-Read or Single-Write waveform. In a FIFO waveform, it

specifies whether a single-data transaction should occur (from/to the SGLDATAH:L or

UDMA_CRCH:L registers), even in a FIFO-Write or FIFO-Read transaction. See also “NEXT/

SGLCRC”, below.

1 = Use SGLDATAH:L or UDMA_CRCH:L.

0 = Use the FIFO.

GINT Bit: specifies whether to generate a GPIFWF interrupt during this State.

1 = Generate GPIFWF interrupt (on INT4) when this State is reached.

0 = Do not generate interrupt.

INCAD Bit: specifies whether to increment the GPIF Address lines GPIFADR[8:0].

1 = Increment the GPIFADR[8:0] bus at the beginning of this State.

0 = Do not increment the GPIFADR[8:0] signals.

NEXT/SGLCRC Bit:

If SGL = 0, specifies whether the FIFO should be advanced at the start of this State.

1 = Move the next data in the OUT FIFO to the top.

0 = Do not advance the FIFO.

The NEXT bit has no effect when the waveform is applied to an IN FIFO.

If SGL = 1, specifies whether data should be transferred to/from SGLDATAH:L or

UDMA_CRCH:L. See also “SGL Bit”, above.

1 = Use UDMA_CRCH:L.

0 = Use SGLDATAH:L.

DATA Bit: specifies whether the FIFO Data bus is to be driven, tristated, or sampled.

During a write:

1 = Drive the FIFO Data bus with the output data.

0 = Tristate (don’t drive the bus).

During a read:

1 = Sample the FIFO Data bus and store the data.

0 = Don’t sample the data bus.

DP Bit: indicates whether the State is a DP or NDP:

1 = Decision Point.

0 = Non-Decision Point.

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