Cypress Semiconductor FX2LP Información técnica descargar pdf (Pagina 259)

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Chapter 11. CPU Introduction Page 11-5

11.6 FX2/DS80C320 Differences

Although the FX2 is similar to the DS80C320 in terms of hardware features and instruction cycle

timing, there are some important differences between the FX2 and the DS80C320.

11.6.1 Serial Ports

The FX2 does not implement serial port framing-error detection and does not implement slave

address comparison for multiprocessor communications. Therefore, the FX2 also does not imple-

ment the following SFRs: SADDR0, SADDR1, SADEN0, and SADEN1.

11.6.2 Timer 2

The FX2 does not implement Timer 2 downcounting mode or the downcount enable bit (TMOD2,

Bit 0). Also, the FX2 does not implement Timer 2 output enable (T2OE) bit (TMOD2, Bit 1). There-

fore, the TMOD2 SFR is also not implemented in the FX2.

The FX2 Timer 2 overflow output is active for one clock cycle. In the DS80C320, the Timer 2 over-

flow output is a square wave with a 50% duty cycle.

Although the T2OE bit is not present in the FX2, Timer 2 output can still be enabled or disabled via

the PORTECFG.2 bit, since the T2OUT pin is multiplexed with PORTE.2.

PORTECFG.2=0 configures the pin as a general-purpose I/O pin and disabled Timer 2 output;

PORTECFG.2=1 configures the pin as the T2OUT pin and enables Timer 2 output.

Table 11-2. Comparison Between FX2 and Other 803x/805x Devices

Feature

Intel

Dallas

DS80C320

Cypress

FX2

8031 8051 80C32 80C52

Clocks per instruction cycle 12 12 12 12 4 4

Program / Data Memory - 4 KB ROM - 8 KB ROM - 8 KB RAM

Internal RAM 128 bytes 128 bytes 256 bytes 256 bytes 256 bytes 256 bytes

Data Pointers 1 1 1 1 2 2

Serial Ports 1 1 1 1 2 2

16-bit Timers 2 2 3 3 3 3

Interrupt sources (internal and

external)

556 6 1313

Stretch data-memory cycles no no no no yes yes

1 2 ... 254 255 256 257 258 259 260 261 262 263 264 ... 459 460

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