Cypress Semiconductor FX2LP Información técnica descargar pdf (Pagina 342)

100

101

EZ-USB FX2 Technical Reference Manual

Page 15-22 EZ-USB FX2 Technical Reference Manual v2.1

15.5.6 230 Kbaud Clock (T0, T1, T2)

Figure 15-15. 230 Kbaud Internally Generated Reference Clock

Bit 1- 0 230UARTx Set 230 KBaud Operation

Setting these bits to 1 overrides the timer inputs to the USARTs, and USART0 and USART1

will use the 230 KBaud clock rate. This mode provides the correct frequency to the USART

regardless of the CPU clock frequency (12, 24, or 48 MHz).

15.5.7 Slave FIFO Interface Pins Polarity

Figure 15-16. Slave FIFO Interface Pins Polarity

Bit 5 PKTEND

FIFO Packet End Polarity

This bit selects the polarity of the PKTEND FIFO input pin. 0 selects the polarity shown in the

data sheet (active low). 1 selects active high.

Bit 4 SLOE FIFO Output Enable Polarity

This bit selects the polarity of the SLOE FIFO input pin. 0 selects the polarity shown in the

data sheet (active low). 1 selects active high.

UART230 230 KBaud clock for T1 E608

b7 b6 b5 b4 b3 b2 b1 b0

0 0 0 0 0 0 230UART1 230UART0

R R R R R R R/W R/W

0 0 0 0 0 0 0 0

FIFOPINPOLAR

see Section 15.14

Slave FIFO Interface Pins Polarity E609

b7 b6 b5 b4 b3 b2 b1 b0

0 0 PKTEND SLOE SLRD SLWR EF FF

R R R/W R/W R/W R/W R/W R/W

0 0 0 0 0 0 0 0

1 2 ... 337 338 339 340 341 342 343 344 345 346 347 ... 459 460

Comentarios a estos manuales

Sin comentarios

Cypress Semiconductor FX2LP Información técnica Pagina 342

Comentarios a estos manuales

Relacionado con productos y manuales para Redes Cypress Semiconductor FX2LP