Cypress Semiconductor FX2LP Información técnica descargar pdf (Pagina 149)

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Chapter 8. Access to Endpoint Buffers Page 8-13

the packet to the outside interface (the “output FIFO”), or discard it. The firmware might, for exam-

ple, inspect a packet header to make this skip/commit decision.

To enable this “hook”, the AUTOOUT bit is cleared to 0. If AUTOOUT = 0 and an OUT endpoint is

re-armed by writing to its low byte-count register, the actual value written to the register becomes

significant:

• If the SKIP bit (bit 7 of each EPxBCL register) is cleared to 0, the packet will be committed

to the output FIFO and thereby made available to the FIFO’s master (either external logic

or the internal GPIF).

• If the SKIP bit is set to 1, the just-received OUT packet will not be committed to the output

FIFO for transfer to the external logic; instead, the packet will be ignored, its buffer will

immediately be made available for the next OUT packet, and the output FIFO (and exter-

nal logic) will never even “know” that it arrived.

The AUTOOUT bit appears in bit 4 of the Endpoint FIFO Configuration Registers EP2FIFOCFG,

EP4FIFOCFG, EP6FIFOCFG and EP8FIFOCFG.

8.6.3 Registers That Control All Endpoints

Table 8-7. Registers that control all endpoints

0xE658 IBNIE IN-BULK-NAK individual interrupt enables

0xE659

IBNIRQ

IN-BULK-NAK individual interrupt requests

0xE65A NAKIE PING plus combined IBN-interrupt enable

0xE65B NAKIRQ PING plus combined IBN-interrupt request

0xE65C USBIE SUTOK, SUDAV, EP0-ACK, SOF interrupt enables

0xE65D

USBIRQ

SUTOK, SUDAV, EP0-ACK, and SOF interrupt requests

0xE65E EPIE Endpoint interrupt enables

0xE65F EPIRQ Endpoint interrupt requests

0xE662

USBERRIE

USB error interrupt enables

0xE663

USBERRIE

USB error interrupt requests

0xE664 ERRCNTLIM USB error counter and limit

0xE665 CLRERRCNT Clear error count

0xE683

TOGCTL

EP0/EP1 data toggle

1 2 ... 144 145 146 147 148 149 150 151 152 153 154 ... 459 460

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