Cypress Semiconductor FX2LP Información técnica descargar pdf (Pagina 164)

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EZ-USB FX2 Technical Reference Manual

Page 9-8 EZ-USB FX2 Technical Reference Manual v2.1

9.2.5 Control Pins (SLOE, SLRD, SLWR, PKTEND, FIFOADR[1:0])

The Slave FIFO “control” pins are SLOE (Output Enable), SLRD (Read), SLWR (Write), PKTEND

(Packet End), and FIFOADR[1:0] (FIFO Select). “Read” and “Write” are from the external master’s

point of view; the external master reads from OUT endpoints and writes to IN endpoints. See

Figure 9-9.

Read — SLOE and SLRD:

In synchronous mode (IFCONFIG.3 = 0), the FIFO pointer is incremented on each rising edge of

IFCLK while SLRD is asserted. In asynchronous mode (IFCONFIG.3 = 1), the FIFO pointer is

incremented on each asserted-to-deasserted transition of SLRD.

The SLOE pin enables the FD outputs.

By default, SLOE and SLRD are active-low; their polarities can be changed via the

FIFOPINPOLAR register.

Write — SLWR:

In synchronous mode (IFCONFIG.3 = 0), data on the FD bus is written to the FIFO (and the FIFO

pointer is incremented) on each rising edge of IFCLK while SLWR is asserted. In asynchronous

mode (IFCONFIG.3 = 1), data on the FD bus is written to the FIFO (and the FIFO pointer is incre-

mented) on each asserted-to-deasserted transition of SLWR.

By default, SLWR is active-low; its polarity can be changed via the FIFOPINPOLAR register.

FIFOADR[1:0]:

The FIFOADR[1:0] pins select which of the four FIFOs is connected to the FD bus (and, if the

FIFO flags are operating in Indexed mode, they select which FIFO’s flags are presented on the

FLAGx pins):

Table 9-2. FIFO Selection via FIFOADR[1:0]

FIFOADR[1:0]

Selected

FIFO

00 EP2

01 EP4

10 EP6

11 EP8

1 2 ... 159 160 161 162 163 164 165 166 167 168 169 ... 459 460

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