Cypress Semiconductor FX2LP Información técnica descargar pdf (Pagina 203)

Chapter 10. General Programmable Interface (GPIF) Page 10-13

To complete a GPIF transaction, the GPIF program must branch to the IDLE State,

regardless of

the State that the GPIF program is currently executing

. For example, a GPIF Waveform might be

defined by a program which contained only 2 programmed States, S0 and S1. The GPIF program

would branch from S1 (or S0) to S7 when it wished to terminate.

The state of the GPIF signals during the Idle State is determined by the contents of the

GPIFIDLECS and GPIFIDLECTL registers.

Once a waveform is triggered, another waveform may not be started until the first one terminates.

Termination of a waveform is signaled through the DONE bit (GPIFIDLECS.7 or GPIFTRIG.7) or,

optionally, through the GPIFDONE interrupt.

• If DONE = 0, the GPIF is busy generating a Waveform.

• If DONE = 1, the GPIF is done (GPIF is in the Idle State) and ready for firmware to start

the next GPIF transaction.

Important:

With one exception (writing to the GPIFABORT register in order to force the current

waveform to terminate) it is illegal to write to any of the GPIF-related registers (including the Wave-

form Registers) while the GPIF is busy. Doing so will cause indeterminate behavior likely to result

in data corruption.

10.3.2.1.1 GPIF Data Bus During IDLE

During the Idle State, the GPIF Data Bus (FD[15:0]) can be either driven or tristated, depending on

the setting of the IDLEDRV bit (GPIFIDLECS.0):

• If IDLEDRV = 0, the GPIF Data Bus is tristated during the Idle State.

• If IDLEDRV = 1, the GPIF Data Bus is actively driven during the Idle State, to the value last

placed on the bus by a GPIF Waveform.

10.3.2.1.2 CTL Outputs During IDLE

During the IDLE State, the state of CTL[5:0] depends on the following register bits:

• TRICTL (GPIFCTLCFG.7), as described in Section 10.2.3.1, "Control Output Modes".

• GPIFCTLCFG[5:0]

• GPIFIDLECTL[5:0].

The combination of these bits defines CTL5:0 during IDLE as follows:

• If TRICTL is 0, GPIFIDLECTL[5:0] directly represent the output states of CTL5:0 during

the IDLE State. The GPIFCTLCFG[5:0] bits determine whether the CTL5:0 outputs are

CMOS or open-drain: If GPIFCTLCFG.x = 0, CTLx is CMOS; if GPIFCTLCFG.x = 1, CTLx

is open-drain.

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Cypress Semiconductor FX2LP Información técnica Pagina 203