Cypress Semiconductor FX2LP Información técnica descargar pdf (Pagina 382)

EZ-USB FX2 Technical Reference Manual

Page 15-62 EZ-USB FX2 Technical Reference Manual v2.1

This register only applies to UDMA IN transactions that are host terminated. Otherwise, this

This register covers a very specific and potentially nonexistent (from a typical system implementa-

tion standpoint*) UDMA CRC situation. However rare the situation may be, it is still allowed by the

ATAPI specification and thus must be considered and solved by this register.

The ATAPI specification says that if the host (in this case the GPIF) terminates a UDMA IN trans-

action, that the device (e.g., the disk drive) is allowed to send up to 3 more words after the host

deactivates the HDMARDY signal. These “dribble” words may not be of interest to the host and

thus may be discarded. However, CRC must still be calculated on them since the host and the

device must compare and match the CRC at the end of the transaction to consider the transfer

error-free.

The GPIF normally only calculates CRC on words that are written into the FIFO (and not dis-

carded). This poses a problem since in this case some words will be discarded but still must be

included in the CRC calculation. This register gives a way to have the GPIF calculate CRC on the

extra discarded words as well.

The user would program this register in the following way. The QENABLE bit would be set to 1.

The QSIGNAL[2:0] field would be programmed to select the CTL pin that coincides with the UDMA

STOP signal. The QSTATE bit would be programmed to be 0. This would instruct the GPIF to cal-

culate CRC on any DSTROBE edges from the device when STOP=0, which solves the problem.

Bit 7 QENABLE

This bit enables the CRC qualifier feature, and thus the other bits in this register.

Bit 3 QSTATE

This bit says what state the CRC qualifier signal (selected by QSIGNAL[2:0] below) must be in

to allow CRC to be calculated on words being written into the GPIF.

Bits 2-0 QSIGNAL[2:0]

These bits select which of the CTL[5:0] pins is the CRC qualifier signal.

* - A typical UDMA system will have the device, instead of the host, terminate UDMA IN trans-

fers thus completely avoiding this situation.

UDMACRCQUALIFIER E67F

b7 b6 b5 b4 b3 b2 b1 b0

QENABLE 0 0 0 QSTATE QSIGNAL[2:0]

RW R R R RW RW RW RW

0 0 0 0 0 0 0 0

1 2 ... 377 378 379 380 381 382 383 384 385 386 387 ... 459 460

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Cypress Semiconductor FX2LP Información técnica Pagina 382