Cypress Semiconductor FX2LP Información técnica descargar pdf (Pagina 140)

EZ-USB FX2 Technical Reference Manual

Page 8-4 EZ-USB FX2 Technical Reference Manual v2.1

– 01 =

invalid

– 10 = double (default)

–11 = triple

“Buffering” refers to the number of RAM blocks available to the endpoint. With double buffering,

for example, USB data can fill or empty an endpoint buffer at the same time that another packet

from the same endpoint fills or empties from the external logic. This technique maximizes perfor-

mance by saving each side, USB and external-logic interface, from waiting for the other side. Mul-

tiple buffering is most effective when the providing and consuming rates are comparable but

bursty (as is the case with USB and many other interfaces, such as disk drives). Assigning more

RAM blocks (triple and quad buffering) provides more “smoothing” of the bursty data rates. A sim-

ple way to determine the appropriate buffering depth is to start with the minimum, then increase it

until no NAKs appear on the USB side and no wait states appear on the interface side.

8.5 CPU Access to FX2 Endpoint Data

Endpoint data is visible to the CPU at the addresses shown in Table 8-3. Whenever the application

calls for endpoint buffers smaller than the physical buffer sizes shown in Tabl e8-3, the CPU

accesses the endpoint data starting from the lowest address in the buffer. For example, if EP2 has

a reported MaxPacketSize of 512 bytes, the CPU accesses the data in the lower portion of the

EP2 buffer (i.e., from 0xF000 to 0xF1FF). Similarly, if the FX2 is operating in full speed mode

(which dictates a maximum Bulk packet size of only 64 bytes), only the lower 64 bytes of the end-

point (i.e., 0xF000-0xF03F for EP2) will be used for Bulk data.

EP0BUF is for the (optional) data stage of a CONTROL transfer. The eight bytes of data from the

CONTROL packet appear in a separate FX2 RAM buffer called SETUPDAT, at 0xE6B8-0xE6BF.

The CPU can only access the “active” buffer of a multiple-buffered endpoint. In other words, firm-

ware must treat a quad-buffered 512-byte endpoint as being only 512 bytes wide, even though the

quad-buffered endpoint actually occupies 2048 bytes of RAM. Also, when EP2 and EP6 are con-

figured such that EP4 and/or EP8 are unavailable, the firmware must never attempt to access the

buffers corresponding to those unavailable endpoints.

Table 8-3. Endpoint Buffers in RAM Space

Name Address Size (bytes)

EPOBUF

0xE740-0xE77F 64

EP1OUTBUF

0xE780-0xE7BF 64

EP1INBUF 0xE7C0-0xE7FF 64

EP2FIFOBUF 0xF000-0xF3FF 1024

EP4FIFOBUF

0xF400-0xF5FF 512

EP6FIFOBUF 0xF800-0xFBFF 1024

EP8FIFOBUF 0xFC00-0xFDFF 512

1 2 ... 135 136 137 138 139 140 141 142 143 144 145 ... 459 460

Sin comentarios

Cypress Semiconductor FX2LP Información técnica Pagina 140