Cypress Semiconductor FX2LP Información técnica descargar pdf (Pagina 142)

EZ-USB FX2 Technical Reference Manual

Page 8-6 EZ-USB FX2 Technical Reference Manual v2.1

HSNAK

HSNAK is automatically set to 1 whenever the SETUP token of a CONTROL transfer arrives. The

FX2 logic automatically NAKs the STATUS (handshake) stage of the CONTROL transfer until the

firmware clears the HSNAK bit by writing “1” to it. This mechanism gives the firmware a chance to

hold off subsequent transfers until it completes the actions required by the CONTROL transfer.

Firmware must clear the HSNAK bit after servicing every CONTROL transfer.

BUSY

The read-only BUSY bit is relevant only for the data stage of a CONTROL transfer. BUSY=1 indi-

cates that the endpoint is currently being serviced by USB, so firmware should not access the end-

point data.

BUSY is automatically cleared to 0 whenever the SETUP token of a CONTROL transfer arrives.

The BUSY bit is set to 1 under different conditions for IN and OUT transfers.

For IN transfers, FX2 logic will NAK all IN0 tokens until the firmware has “armed” EP0 for IN trans-

fers by writing to the EP0BCH:L Byte Count register, which sets BUSY=1 to indicate that firmware

should not access the data. Once the endpoint data is sent and acknowledged, BUSY is automat-

ically cleared to 0 and the EP0IN interrupt request bit is asserted. After BUSY is automatically

cleared to 0, the firmware may refill the EP0IN buffer.

For OUT transfers, FX2 logic will NAK all OUT0 tokens until the firmware has “armed” EP0 for

OUT transfers by writing any value to the EP0BCL register. BUSY is automatically set to 1 when

the firmware writes to EP0BCL, and BUSY is automatically cleared to 0 after the data has been

correctly received and ACK’d. When BUSY transitions to zero, the FX2 also generates an

EP0OUT interrupt request.

The FX2’s autovectored interrupt system automatically transfers control to the appropriate ISR

(Interrupt Service Routine) for the endpoint requiring service. Chapter 4, "Interrupts" describes this

mechanism.

STALL

Set STALL=1 to instruct the FX2 to return the STALL response to a CONTROL transfer. This is

generally done when the firmware does not recognize an incoming USB request. According to the

USB spec, endpoint zero must always accept transfers, so STALL is automatically cleared to 0

whenever a SETUP token arrives. If it’s desired to stall a transfer and also clear HSNAK to 0 (by

writing a 1 to it), the firmware should set STALL=1 first, in order to ensure that the STALL bit is set

before the “acknowledge” phase of the CONTROL transfer can complete.

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Cypress Semiconductor FX2LP Información técnica Pagina 142