
Chapter 10. General Programmable Interface (GPIF) Page 10-7
10.2.3 Six Control OUT Signals
The 100- and 128-pin FX2 packages bring out all six Control Output pins, CTL[5:0]. The 56-pin
package brings out three of these signals, CTL[2:0]. CTLx waveform edges can be programmed to
make transitions as often as once per IFCLK clock (once every 20.8 ns if IFCLK is running at
48MHz).
By default, these signals are driven high.
10.2.3.1 Control Output Modes
The GPIF Control pins (CTL[5:0]) have several output modes:
• CTL[3:0] can act as CMOS outputs (optionally tristatable) or open-drain outputs.
• CTL[5:4] can act as CMOS outputs or open-drain outputs.
If CTL[3:0] are configured to be tristatable, CTL[5:4] are not available.
10.2.4 Six Ready IN signals
The 100- and 128-pin FX2 packages bring out all six Ready inputs, RDY[5:0]. The 56-pin package
brings out two of these signals, RDY[1:0].
The RDY inputs can be sampled synchronously or asynchronously. When the GPIF is in asynchro-
nous mode (SAS=1), the RDY inputs are unavoidably delayed by a small amount (approximately
24 ns at 48 MHz IFCLK). In other words, when the GPIF “looks” at a RDY input, it actually “sees”
the state of that input 24 ns ago.
10.2.5 Nine GPIF Address OUT signals
Nine GPIF address lines, GPIFADR[8:0], are available. If the GPIF address lines are configured as
outputs, writing to the GPIFADRH:L registers drives these pins immediately. The GPIF engine can
then increment them under control of the Waveform Descriptors. The GPIF address lines can be
tristated by clearing the associated PORTxCFG bits and OEx bits to 0 (see Section 13.3.3, "Port C
Alternate Functions" and Section 13.3.4, "Port E Alternate Functions").
Table 10-3. CTL[5:0] Output Modes
TRICTL
(GPIFCTLCFG.7)
GPIFCTLCFG[6:0] CTL[3:0] CTL[5:4]
0 0 CMOS, Not Tristatable CMOS, Not Tristatable
0 1 Open-Drain Open-Drain
1 X CMOS, Tristatable Not Available
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