Cypress Semiconductor FX2LP Información técnica descargar pdf (Pagina 52)

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EZ-USB FX2 Technical Reference Manual

Page 1-26 EZ-USB FX2 Technical Reference Manual v2.1

Figure 1-16. FX2 FIFOs in “Slave FIFO” Mode

Figure 1-16 illustrates the outside-world view of the FX2 data FIFOs configured as “Slave FIFOs”.

The outside logic supplies a clock, responds to the FIFO flags, and clocks FIFO data in and out

using the strobe signals. Optionally, the outside logic may use the internal FX2 Interface Clock

(IFCLK) as its reference clock.

Three FIFO flags are shown in parentheses in Figure1-16 because they actually are called

FLAGA-FLAGD in the pin diagram (there are four flag pins). Using configuration bits, various FIFO

flags can be assigned to these general-purpose flag pins. The names shown in parentheses illus-

trate typical uses for these configurable flags. The Programmable Level Flag (PRGFLAG) can be

set to any value to indicate degrees of FIFO “fullness”. The outside interface selects one of the

four FIFOs using the FIFOADR pins, and then clocks the 16-bit FIFO data using the SLRD (Slave

Read) and SLWR (Slave Write) signals. PKTEND is used to dispatch a non-full IN packet to USB.

Synchronous

Asynchronous

SLRD

SLWR

PKTEND

IFCLK

SLRD

SLWR

PKTEND

FIFO

FD[15:0]

Data

(OUTEMPTY)

(INFULL)

(PRGFLAG)

IFCLK

SLRD

SLWR

SLOE

PKTEND

FIFOADR1

FIFOADR0

EP8

EP6

EP4

EP2

select

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