Cypress Semiconductor FX2LP Información técnica descargar pdf (Pagina 257)

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Chapter 11. CPU Introduction Page 11-3

11.3 Performance Overview

The FX2 has been designed to offer increased performance by executing instructions in a 4-clock

bus cycle, as opposed to the 12-clock bus cycle in the standard 8051 (see Figure 11-2). This short-

ened bus timing improves the instruction execution rate for most instructions by a factor of three

over the standard 8051 architectures.

Some instructions require a different number of instruction cycles on the FX2 than they do on the

standard 8051. In the standard 8051, all instructions except for MUL and DIV take one or two

instruction cycles to complete. In the FX2, instructions can take between one and five instruction

cycles to complete. However, due to the shortened bus timing of the FX2, every instruction exe-

cutes faster than on a standard 8051, and the average speed improvement over the entire instruc-

tion set is approximately 2.5×. Table 11-1 catalogs the speed improvements.

Table 11-1. FX2 Speed Compared to Standard 8051

Of the 246 FX2 opcodes...

150 execute at 3.0× standard speed

51 execute at 1.5× standard speed

43 execute at 2.0× standard speed

2 execute at 2.4× standard speed

Average Improvement: 2.5×

Note: Comparison is between FX2 and standard 8051 run-

ning at the same clock frequency.

1 2 ... 252 253 254 255 256 257 258 259 260 261 262 ... 459 460

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Cypress Semiconductor FX2LP Información técnica Pagina 257

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