Cypress Semiconductor FX2LP Información técnica descargar pdf (Pagina 301)

Chapter 14. Timers/Counters and Serial Interface Page 14-9

14.2.4.1 Timer 2 Mode Control

Table 14-6 summarizes how the T2CON bits determine the Timer 2 mode.

Table 14-5. T2CON Register — SFR 0xC8

Bit Function

T2CON.7 TF2 - Timer 2 overflow flag. Hardware will set TF2 when the Timer 2 overflows from 0xFFFF.

TF2 must be cleared to 0 by the software. TF2 will only be set to a 1 if RCLK and TCLK are

both cleared to 0. Writing a 1 to TF2 forces a Timer 2 interrupt if enabled.

T2CON.6 EXF2 - Timer 2 external flag. Hardware will set EXF2 when a reload or capture is caused by

a high-to-low transition on the T2EX pin, and EXEN2 is set. EXF2 must be cleared to 0 by

software. Writing a 1 to EXF2 forces a Timer 2 interrupt if enabled.

T2CON.5 RCLK - Receive clock flag. Determines whether Timer 1 or Timer 2 is used for Serial Port 0

timing of received data in serial mode 1 or 3. RCLK=1 selects Timer 2 overflow as the

receive clock; RCLK=0 selects Timer 1 overflow as the receive clock.

T2CON.4 TCLK - Transmit clock flag. Determines whether Timer 1 or Timer 2 is used for Serial Port 0

timing of transmit data in serial mode 1 or 3. TCLK=1 selects Timer 2 overflow as the trans-

mit clock; TCLK=0 selects Timer 1 overflow as the transmit clock.

T2CON.3 EXEN2 - Timer 2 external enable. EXEN2=1 enables capture or reload to occur as a result of

a high-to-low transition on the T2EX pin, if Timer 2 is not generating baud rates for the serial

port. EXEN2=0 causes Timer 2 to ignore all external events on the T2EX pin.

T2CON.2 TR2 - Timer 2 run control flag. TR2=1 starts Timer 2; TR2=0 stops Timer 2.

T2CON.1 C/T

2 - Counter/Timer select. When C/T2 = 1, Timer 2 is clocked by high-to-low transitions on

the T2 pin.When C/T

2 = 0 in modes 0, 1, or 2, Timer 2 is clocked by CLKOUT/4 or CLKOUT/

12, depending on the state of T2M (CKCON.5). When C/T

2 = 0 in mode 3, Timer 2 is

clocked by CLKOUT/2, regardless of the state of CKCON.5.

T2CON.0 CP/RL

2 - Capture/reload flag. When CP/RL2=1, Timer 2 captures occur on high-to-low tran-

sitions of the T2EX pin, if EXEN2 = 1. When CP/RL

2 = 0, auto-reloads occur when Timer 2

overflows or when high-to-low transitions occur on the T2EX pin, if EXEN2 = 1. If either

RCLK or TCLK is set to 1, CP/RL

2 will not function and Timer 2 will operate in auto-reload

mode following each overflow.

Table 14-6. Timer 2 Mode Control Summary

TR2 TCLK RCLK CP/RL2 Mode

0 X X X Timer 2 stopped

1 1 X X Baud rate generator

1 X 1 X Baud rate generator

1 0 0 0 16-bit timer/counter with auto-reload

1 0 0 1 16-bit timer/counter with capture

X = Don’t care

1 2 ... 296 297 298 299 300 301 302 303 304 305 306 ... 459 460

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