Cypress Semiconductor FX2LP Información técnica descargar pdf (Pagina 143)

Chapter 8. Access to Endpoint Buffers Page 8-7

8.6.1.2 EP0BCH and EP0BCL

These are the byte count registers for bytes sent as the optional data stage of a CONTROL trans-

fer. Although the EP0 buffer is only 64 bytes wide, the byte count registers are 16 bits wide to allow

using the Setup Data Pointer to send USB IN data records that consist of multiple packets.

To use the Setup Data Pointer in its most-general mode, firmware clears the SUDPTR AUTO bit

and writes the address of a data block into the Setup Data Pointer, then loads the EP0BCH:L reg-

isters with the total number of bytes to transfer. The FX2 automatically transfers the entire block,

partitioning the data into MaxPacketSIze packets as necessary.

The Setup Data Pointer is the subject of Section 8.7.

For IN transfers without using the Setup Data Pointer, firmware loads data into EP0BUF, then

writes the number of bytes to transfer into EP0BCH and EP0BCL. The packet is armed for IN

transfer when the firmware writes to EP0BCL, so EP0BCH should always be loaded first. These

transfers are always 64 bytes or less, so EP0BCH must be loaded with 0 (and EP0BCL must be in

the range [0-64]). EP0BCH will hold that zero value until firmware overwrites it.

For EP0 OUT transfers, the byte count registers indicate the number of bytes received in EP0BUF.

Byte counts for EP0 OUT transfers are always 64 or fewer, so EP0BCH is always zero after an

OUT transfer. To re-arm the EP0 buffer for a future OUT transfer, the firmware simply writes any

value to EP0BCL.

The EP0BCH register must be initialized on reset, since its power-on-reset state is undefined.

8.6.1.3 USBIE, USBIRQ

Three interrupts — SUTOK, SUDAV, and EP0ACK — are used to manage CONTROL transfers

over endpoint zero. The individual enables for these three interrupt sources are in the USBIE reg-

ister, and the interrupt-request flags are in the USBIRQ register.

Each of the three interrupts signals the completion of a different stage of a CONTROL transfer.

• SUTOK (“Setup Token”) asserts when FX2 receives the SETUP token.

• SUDAV (“Setup Data Available”) asserts when FX2 logic has loaded the eight bytes from

the SETUP stage into the 8-byte buffer at SETUPDAT.

• EP0ACK (“Endpoint Zero Acknowledge”) asserts when the handshake stage has com-

pleted.

The SUTOK interrupt is not normally used; it is provided for debug and diagnostic purposes. Firm-

ware generally services the CONTROL transfer by responding to the SUDAV interrupt, since this

interrupt fires only after the 8 setup bytes are available for examination in the SETUPDAT buffer.

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Cypress Semiconductor FX2LP Información técnica Pagina 143