Cypress Semiconductor ISR 37000 CPLD Especificaciones descargar pdf (Pagina 9)

Design Considerations for ISR Programming of Cypress CPLDs

Device-Specific ISR Design Considerations

The In-System Reprogammability feature is available on a

wide range of Cypress programmable devices. While the

board layout recommendations discussed herein apply to all

ISR devices, there are some notable ISR design consider-

ations that are distinct for each family.

Board-level design issues addressed in this section include:

the state of ISR programming pins when floating, bus-hold pin

differences between the F

LASH

370i and the Ultra37000, and

supported I/O levels for JTAG signaling.

The Delta39K, Quantum38K, PSI, and Ultra37000 ISR device

families incorporate internal weak pull-ups on the JTAG pins

TDI and TMS as required by the IEEE 1149.1 specification.

This is to ensure that, if a solder fault results in an open circuit

on a JTAG pin, the internal TAP controller in the device will

enter the predictable, safe Test-Logic-Reset state. The

LASH

370i family has a bus-hold structure on these pins.

While still JTAG compliant, this family alone does not support

boundary scan capability.

It is important to consider that noise from a large number of

I/Os switching simultaneously during boundary scan opera-

tions can affect functionality. Therefore, it is highly recom-

mended that these boundary scan tests be done in a relative-

ly low noise environment.

Delta39K/Quantum38K/PSI Families

The Delta39K, Quantum38K and PSI families permit flexible

signal levels on the ISR pins, including 3.3V, 2.5V, and 1.8V,

supporting LVTTL, LVCMOS, LVCMOS2, and LVCMOS18 I/O

standards.

Each voltage can be selected by applying the de-

sired target voltage to the V

CCJTAG

pin. The recommended

voltage for JTAG port signals is 3.3V. These devices have

single-function dedicated JTAG pins.

Since these families lack 5V tolerance, they cannot directly be

driven by 5V levels without additional board components.

Consequently, Delta39K, Quantum38K, and PSI devices can-

not directly follow an Ultra37000 or a F

LASH

370i device driving

5V within a scan chain cascade, since TDI will violate input

voltage specs. Board-level solutions for interfacing Delta39K,

Quantum38K or PSI I/Os to 5V is described in the Cypress

application note: “Interfacing Delta39K and Quantum38K

CPLDs to 5V Devices.”

These families, based on volatile SRAM technology, require

configuration at power-up prior to normal operation. I/Os are

enabled only after configuration is complete. Up to this time,

I/Os are three-stated and can be subjected to live signals. For

the case of a self-boot solution, the initial data stored on the

internal FLASH ensures I/Os three-state after device config-

uration completes. For volatile devices requiring external con-

figuration, they will continually restart configuration cycles un-

til either a valid configuration bitstream is downloaded from

the boot EEPROM or JTAG instructions program the part.

More information on Delta39K configuration can be found in

the Cypress application note: “Configuring

Delta39K/Quantum38K.”

Ultra37000 Family

Ultra37000 devices support 5V or 3.3V I/Os (including the

ISR pins) since the I/O power supply, V

CCIO

, is split from the

core power supply. Ultra37000V devices support only 3.3V,

yet have I/Os which are tolerant to 5V inputs.

Ultra37000 CPLDs differ from Delta39K in that certain device

packages offer dual-function pins that operate as ISR signals

in programming mode or as regular input/output in I/O mode.

These are typically smaller packages with a restricted pin

count. For these dual-function devices, the pin called JTAGen

controls the multiplex between modes. When programming

(JTAGen is HIGH), JTAGen enables the ISR interface for dual-

mode devices. When the JTAGen signal disables the ISR in-

terface (JTAGen is LOW), the ISR device will start driving

some of its output pins, based upon the functionality of the

design.

The user can configure a dual-function pin as an input, output,

or bidirectional input/output. This requires additional external

logic to mediate between JTAG signals and I/O signals. This

external logic requirement is discussed in detail in Appendix

While specific F

LASH

370i devices also support dual-mode

pins, there are small differences between ISRen for

LASH

370i and JTAGen for Ultra37000 to take into consider-

ation. Simple cascading of single- and dual-function devices

of both families is discussed in Appendix B.

State of ISR Pins When the ISR Pins Float for Ultra37000

Devices

The ISR pins can be floating if, for example, a programming

cable is not attached to the on-board ISR header. The only

ISR programming difference between the Ultra37000 and

LASH

370i family is the connection of the bus-hold latches on

the ISR interface pins. Specifically, for Ultra37000 CPLDs the

bus-hold latches are disconnected from the JTAG pins TCK,

TMS, TDI, and TDO when the JTAGen pin is HIGH, thereby

enabling the JTAG port. The bus-hold latches are connected

when the JTAGen pin is LOW, thereby disabling the JTAG

port. For the single-function devices there is no JTAGen pin

and the ISR interface is permanently enabled; therefore, the

bus-hold latches for JTAG pins are permanently disabled.

These differences allow the Ultra37000 family to support

JTAG Boundary Scan testing. (Bus-hold latches could have

caused significant DC loading on the JTAG drivers of TCK and

TMS depending on the source impedance of the drivers and

the number of devices connected in the ISR chain. This could

occur because these signals, TCK and TMS, are connected

in parallel to all the devices in the ISR chain.)

An additional difference is that internal pull-up resistors are

enabled on the TDI and TMS JTAG pins when the ISR inter-

face is enabled. This change allows conformance to the IEEE

1149.1 specification and is necessary to place the Test Ac-

cess Port (TAP) controller of a JTAG device in a known benign

state such as Test-Logic-Reset if solder open faults occur in

the ISR chain. The bus-hold latch is still permanently enabled

on the JTAGen pin and powers up in the HIGH state. To de-

termine whether external resistors are needed we once again

must consider the single- and dual-function mode cases.

For single-function mode devices the only pin that needs an

external resistor pull-down is the TCK pin since there are al-

ready internal pull-ups for TDI and TMS and the TDO pin is a

dedicated output pin.

For dual-function mode devices operating in single-function

mode or dual-function mode no external pull-ups are neces-

sary since the bus-hold latches are reconnected to the ISR

pins once the ISR interface is disabled.

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