Cypress Semiconductor ISR 37000 CPLD Especificaciones descargar pdf (Pagina 2)

Design Considerations for ISR Programming of Cypress CPLDs

TMS (SMODE) – Mode Control

During programming, this is the mode control input that di-

rects the Test Access Port (TAP) controller state machine con-

tained within the ISR interface on the device.

JTAGen (ISRen) – Enables the 4-pin JTAG Interface

This pin is present on packages of Ultra37000(V) or

LASH

370i devices where the JTAG pins share their function-

ality with I/O pins. Dual-mode device details are found in Ap-

pendix A. For the Ultra37000(V), when the JTAGen pin is at a

TTL HIGH level the JTAG pin functionality is selected. When

it is at a TTL LOW level the I/O pin functionality is selected.

For the F

LASH

370i devices the JTAG pin functionality is select-

ed when it is at a supervoltage of 12.0V and the I/O pin func-

tionality is selected when it is at a TTL LOW level. This func-

tional difference in the JTAGen pin for these two ISR device

families is important and is discussed later in this application

note. All other ISR device families do not use JTAGen.

ISR* – Indicates Active ISR Operation Taking Place

This additional signal is not used by any CPLD device for

programming. Rather, it is present on the ISR header to allow

the programming source (e.g., ISR PC cable) to signal to the

user’s board when ISR operations are occurring. This can be

useful for monitoring purposes or for user logic that controls

any dual-function ISR pins of specific Ultra37000(V) or

LASH

370i devices, as discussed in Appendix A. If on-board

logic uses this signal, ISR* should be pulled-up to V

through a pull-up resistor on the circuit board to handle the

case when no cable is attached.

The ISR Programming Cables

The simplest method to program ISR devices is to use a PC

as shown in Figure 1. The ISR programming cable connects

the parallel port of the PC to a cable header on the user’s

board where the ISR devices are soldered. The header on the

user’s board connects to traces that route to the JTAG pins on

the ISR device itself. The ISR software runs on the PC and

drives these pins on the board, through the cable and header,

to program the devices with the appropriate bitstream.

Since each cable contains active components that buffer sig-

nals driven between the user’s board and the PC, the cable

must receive power from the user’s board. It is recommended

that the PC be powered-off prior to plugging in an ISR PC

cable.

Table 1 shows the available Cypress ISR programming cables

and their appropriate usage.

Figure 1. ISR Programming Set-up using a PC

TO PARALLEL PORT

ISR PROGRAMMING CABLE

TO 10–PIN CONNECTOR ON BOARD

Table 1. Available ISR PC Programming Cables

Programming Cable Part Number Supported ISR Signal Voltages Supported Devices

C3ISR C3ISR.02 (rev. 0.02) 5V, 3.3V, 2.5V, 1.8V Delta39K, Quantum38K, PSI,

Ultra37000, Ultra37000V

UltraISR 37KISR.03 (rev. 0.03) 5V, 3.3V Delta39K, Quantum38K, PSI,

Ultra37000, Ultra37000V

ISRPCCABLE ISRPCCABLE.03A

(rev 0.03A)

(with 12V supervoltage on ISRen)

LASH

370i, Ultra37000

(Ultra37000V not supported)

1 2 3 4 5 6 7 ... 19 20

Comentarios a estos manuales

Sin comentarios

Cypress Semiconductor ISR 37000 CPLD Especificaciones Pagina 2

Comentarios a estos manuales

Relacionado con productos y manuales para No Cypress Semiconductor ISR 37000 CPLD