Cypress Semiconductor ISR 37000 CPLD Especificaciones descargar pdf (Pagina 20)

Design Considerations for ISR Programming of Cypress CPLDs

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

Appendix C. Additional F

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370i Family Design Considerations

This appendix describes additional F

LASH

370i device and

board-level design considerations not covered in the

LASH

370i device-specific section of this application note.

State of ISR Programming Pins When the ISR Pins Float for

LASH

370i Devices

The ISR pins can be floating if, for example, a programming

cable is not attached to the on-board ISR header. The ISR

programming cable is only plugged into the connector on your

board during programming; however, it is acceptable to float

the ISR pins for the F

LASH

370i devices when the board is

powered up and operating. This is acceptable because the

ISR devices have been designed with bus-hold structures on

every input, input/clock, and I/O pin, including the program-

ming pins for both dual-function and single-function devices.

The exception to this is the TDO pin on single-function devic-

es, which is an output only and the JTAGen pin, which may

incorporate a pull-down device instead of a bus-hold latch.

The bus-hold latch eliminates the need to use external pull-

up resistors or any other technique for handling the case

where the ISR programming pins are left floating due to the

ISR programming cable being disconnected.

Bus-hold structures enable a pin to maintain its most recent

logic value even when it is three-stated, whether that value

was being driven in as an input pin or driven out as an output

pin. This is done with a weak latch connected to the pin. Since

the ISR programming pins have bus-hold structures, when

the ISR programming cable is disconnected and the board is

powered on, the ISR programming pins all maintain a logic

LOW or logic HIGH value even though they are no longer

being driven. If the ISR programming cable is disconnected

when the board is powered-down, or if the board is powered-

down and then back up after the cable has been disconnect-

ed, there is still no problem. The ISR bus-hold structures have

been designed to always power-up with a logic HIGH level

maintained on the pins to emulate an internal pull-up.

The utility of the bus-hold structures applies both to the case

of ISR programming pins used as single-function pins and as

dual-function pins. The bus-hold latch does not interfere with

the normal function of the pin because of the relative weak-

ness of the latch to the output driver. The latch is more than

50 times weaker than the ISR device’s output driver.

Note that the ISR* pin from the ISR programming cable con-

nector does not connect to an ISR device pin. Since it does

not, you must use a pull-up on the ISR* signal on your board

so that it is not left floating when the ISR programming cable

is disconnected. This signal can be used to support dual-

mode JTAG/IO pins or to simply monitor when programming

operations are taking place.

State of the ISR Programming Pins When the ISR

Programming Cable is Not Attached for Both Ultra37000

Devices and F

LASH

370i Devices in the Same ISR Chain

For the case where both single-function mode Ultra37000

and F

LASH

370i devices are in the ISR programming chain, no

external resistor is needed even on the TCK pin. This is be-

cause these pins are connected in parallel to all devices in the

chain and the bus-hold latches, which are always present on

the F

LASH

370i devices, hold the pin to a logic LOW or HIGH

level preventing it from floating.

Handling the 12V Signal on the Board for F

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370i Devices

Unlike the Ultra37000 family, in which the JTAGen signal

serves only to choose either JTAG or I/O function on the dual-

function pins, F

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370i devices uses this pin as the high-

voltage, low-impedance path required for programming the

device. There are two requirements on the ISRen program-

ming voltage that necessitate special handling when pro-

gramming F

LASH

370i devices. The first is that its voltage must

be in the range 11.4V

ISRen

12.6V during programming,

and the second is that its maximum transient current is 40 mA

per ISR device during programming. The 5V/12V DC/DC con-

verter and other components in the ISR programming cable

described in this application note have been chosen to ensure

that these specifications are met. Therefore it is suggested

that the 12V supplied by the ISR cable be used for program-

ming rather than another 12V supply that may be available on

the board.

Due to the higher than usual current and voltage require-

ments on the ISRen signal, the trace on the printed-circuit

board connecting the ISRen pin from the ISR programming

cable to the ISRen pin on the F

LASH

370i device(s) also de-

serves special attention. First, to handle the current, the trace

should be double the width of the standard traces. Second,

the trace should be kept as short as possible. In general, this

means the connector for the ISR programming cable should

be placed as close as possible to the F

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370i devices on

the board. Since the connector is small, it is much easier to

move the connector closer to the devices than change the

whole board layout to place the devices close to the chosen

spot for the connector.

Decoupling the ISRen Pin to Ground for F

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370i Devices

One further board layout recommendation is to place a 10-nF

capacitor located at the 10-pin header connector on the circuit

board on the JTAGen pin to ground if there are F

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370i

devices to be programmed on the board. If proper ISR cable

connection procedures explained in this application note are

followed this capacitor is not needed. If the ISR cable is hot-

socket connected to the user’s board, which is not recom-

mended, then this capacitor insures that a proper, slow ramp-

ing 12V is applied to the devices to be programmed under all

operating conditions with no risk of damage to the JTAGen

pin. Since the ISR cable could easily be hot-socket connected

by accident, it is advisable and simple to incorporate this de-

coupling capacitor.

In-System Reprogrammable, ISR, F

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370i, Delta39K, Quantum38K, Ultra37000, Programmable Serial Interface, and PSI are

trademarks and Warp is a registered trademark of Cypress Semiconductor Corporation.

PAL is a registered trademark of Advanced Micro Devices.

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