Cypress Semiconductor ISR 37000 CPLD Especificaciones descargar pdf (Pagina 13)

Design Considerations for ISR Programming of Cypress CPLDs

ers or pass-transistors from a 74FCT244T or a Texas Instru-

ments SN74CBT3384A, for example, to implement the logic

shown in Figure 14(b). The connections for the FCT257T,

FCT244T, and SN74CBT3384A are shown in Figure 14(c),

(d), and (e), respectively. To reduce unnecessary noise it is a

good idea to tie the unused inputs on the FCT devices to

ground instead of letting them float.

The inverter shown in Figure 14(e) can be eliminated by im-

plementing an inversion within the SN74CBT3384A device.

This requires using only an external resistor and a few addi-

tional connections. An inversion of the connection to pin BE1*

is accomplished by connecting +5V to pin A1 and connecting

one end of a resistor to GND and the other end to pin B1. B1

is then the inverse of the input connected to BE1*, which is

Figure 14. Design for Dual-Function Pins: TDI/TCK/TMS used with Input

TDI

Signal

ISR*

TDI/IO

ISR

(a) Multiplexer Solution

TDI

Signal

ISR*

TDI/IO

ISR

(b) Buffer Solution

ISR

ISR*

TDI

Signal

TDI/IO

FCT257T

DIP/SOIC/QSOP

I0a

I1a

ISR

ISR*

TDI

Signal

TDI/IO

FCT244T

DIP/SOIC/QSOP

OA0

OB0

OEA

OEB

DA0

DB0

(d) FCT244T Implementation

ISR*

TDI

Signal

TDI/I/O

SN74CBT3384A

DIP/SOIC/QSOP

ISR

BE1

BE2

(e) SN74CBT3384A Implementation

TDI/IO

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 19 20

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