Cypress Semiconductor ISR 37000 CPLD Especificaciones descargar pdf (Pagina 5)

Design Considerations for ISR Programming of Cypress CPLDs

To program a single ISR device using any ISR programming

cable described here, route the TDI, TDO, TCK, TMS, and

JTAGen pins from the cable connector to the TDI, TDO, TCK,

TMS, and JTAGen (if present on the package) pins of the ISR

device, respectively. If no ISR devices use JTAGen, this pin

can float. Multiple devices can be programmed in a single ISR

programming chain, explained later in this application note.

For multiple devices in the chain, the TDI and TDO pins are

connected in a serial chain such that the TDO of the first de-

vice in the chain connects to the TDI of the next device in the

chain. The TDO of the last device in the chain then returns

back to the 10-pin header TDO pin.

In addition to these programming pins, there is an additional

signal available from the cable called ISR*. The purpose of

this signal is to allow the user to monitor when ISR operations

are in progress. If ISR* is a logic LOW, it indicates that

JTAGen is asserted (at 12V supervoltage for F

LASH

370i de-

vices) and ISR operations, such as programming, are in pro-

cess on the board. If ISR* is a logic HIGH, it indicates JTAGen

is 0V and no ISR operations are being performed. The ISR*

pin is needed when using the JTAG/IO pins in both ISR

(JTAG) and functional (IO) modes, as supported by certain

packages of the Ultra37000 and F

LASH

370i families. It is used

by on-board logic to determine when the JTAG signals should

be enabled and other driving signals to the ISR device should

be placed in the high-impedance state (three-stated). This is

discussed in detail in Appendix A. When the ISR cable is con-

nected, this signal is driven appropriately to a HIGH or LOW

level. When the cable is disconnected, the ISR* signal must

be pulled up on the circuit board, using a pull-up resistor to

the V

pin of the ISR connector to indicate to the board that

no ISR operation is in progress.

There are three other connection points on the cable and ca-

ble header: V

, GND, and NC. V

connects to the V

plane on the board containing the ISR devices. It supplies

power to the active components within the ISR cable. This is

necessary for any ISR programming cable to be able to buffer

JTAG signals or translate voltage levels. On the UltraISR PC

cable, V

simply supplies power to the buffer in the cable for

the JTAG signals. On the C3ISR cable, V

from the user’s

board supplies power to the buffer and voltage translation log-

ic of the cable. GND provides a common ground reference

between the board and the ISR programming cable. NC is a

“no connect” pin and is not used. For boards containing both

5V and 3.3V, it is recommended to connect 5V to the V

header pin instead of 3.3V. This doesn’t apply for Delta39K,

Quantum38K, or PSI devices, which cannot tolerate 5V.

Connecting the ISRPCCABLE to the Board

Since the ISRPCCABLE provides a high voltage (12V) to the

device, it is recommended that the ISR cable be plugged into

the PC and the customer’s board before power is applied to

the board. (This is not as important for the C3ISR or UltraISR

PC cables since there are no 12V signals generated in the

cables.) Once the cable is connected, the user can power up

the board. This assures a normal slew rate on the ISRen pin

for all possible conditions. It is also recommended that the

user run the ISR software after the cable is plugged into the

user’s board and PC parallel port. This allows the software to

correctly set the ISR pins to their appropriate initialized state

on the parallel port of the PC. All of the ISR signals are buff-

ered in the ISR cables and are permanently enabled.

With this configuration, it is recommended to place a 10-nF

capacitor located at the 10-pin header connector on the circuit

board from the ISRen pin to ground. If the ISR cable is hot-

socket connected to the user’s board, which is not recom-

mended, then this capacitor insures that a proper, slow ramp

up to 12V is applied to the devices to be programmed under

all operating conditions, with no risk of damage to the ISRen

pin. Since the ISR cable could easily be hot-socket connected

by accident, it is advisable and simple to incorporate this de-

coupling capacitor. Again, this only applies if the

ISRPCCABLE is used.

Simple ISR Device Cascading

You can cascade many ISR devices in a system. That is, you

can daisy-chain the devices together and connect their pro-

gramming pins in such a way that all devices can be pro-

grammed from a single connection to the ISR programming

source.

To do this, simply tie all of the TCK and TMS pins (and

JTAGen if present) of each device to the corresponding pins

of the ISR connector. You then connect the TDI pin from the

connector to the TDI pin of the first device in the chain, then

connect the TDO output of that device to the TDI input of the

next device in the chain, and so forth, until you finally connect

the TDO output of the last device in the chain to the TDO pin

of the cable connector or other programming source (see Fig-

ure 6).

Cascading With Other IEEE 1149.1-Compliant Devices

Other vendor IEEE 1149.1-compliant devices can be included

in the chain. The ISR programming software will load the non-

Cypress device’s instruction register with the proper BYPASS

instruction.

Cascading Ultra37000 and F

LASH

370i ISR Devices

In addition to the optional external circuitry required to take

advantage of dual JTAG/IO functions per dual-mode ISR de-

vice, the JTAGen pin has slightly different functionality be-

tween the F

LASH

370i and the Ultra37000 families. For details

on Ultra37000 and F

LASH

370i cascading, see Appendix B.

Figure 6. Simple Cascading of ISR Devices

TDI TDO

TMS

TCK

ISR Device

TDI TDO

TMS

TCK

ISR Device

TDI TDO

TMS

TCK

Other JTAG

Compliant

Device

TDI

TDO

TCK

TMS

1 2 3 4 5 6 7 8 9 10 ... 19 20

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