Cypress Semiconductor ISR 37000 CPLD Especificaciones Pagina 10

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Design Considerations for ISR Programming of Cypress CPLDs
10
The value of this pull-down resistor for TCK is not crucial since
the external JTAG pin driver simply has to be strong enough
to overpower the resistor. Typical values are 10 k or 4.7k.
F
LASH
370i Family
Like the Ultra37000 family, F
LASH
370i CPLDs have a separate
I/O power supply, V
CCIO
, which can support 5V or 3.3V levels.
Only the ISRPCCABLE can program an ISR chain containing
F
LASH
370i devices. This is because this cable alone produces
the required 12V supervoltage on the ISRen pin required for
device programming. This cable, however, does not support
3.3V ISR signaling so it cannot be used with any 3.3V ISR
device like the Delta39K.
Smaller F
LASH
370i packages contain pins which offer dual-
mode functionality between ISR programming mode and nor-
mal I/O mode, similar to the Ultra37000 family. The necessary
external logic to support dual functionality is detailed in Ap-
pendix A. Specific design considerations with cascading sin-
gle- and dual-function Ultra37000 and F
LASH
370i devices are
found in Appendix B.
Additional F
LASH
370i device and board-level design consider-
ations are found in Appendix C.
State of General Cypress ISR Device I/Os at Power-Up
When ISR devices are shipped from Cypress, the devices
have already been programmed, erased, and programmed
again as part of the testing process. They will not, therefore,
be blank when they first come out of the tube. They will, how-
ever, be programmed such that all of the I/Os are three-stated
after power-up. Furthermore, all I/Os (except TDO) are three-
stated during device programming. This allows soldering of
ISR devices directly onto a users board without having to
erase them first. It allows the user to power-up a board and
program the ISR devices on it without worrying whether their
initial, non-blank state will cause any problems such as output
contention with other devices on the board.
The ISR programming procedure is to take ISR devices di-
rectly from the tube, solder them onto the board, connect the
programming source (such as the ISR programming cable
attached to a PC), turn on the power to the board, and then
program the devices for the first time. Since many of the I/Os
on the ISR device(s) are undoubtedly inputs, other devices on
the board could be driving those pins immediately upon pow-
ering up the system. By having all of the ISR I/Os initially
programmed to be three-stated, and by guaranteeing the
same three-state during ISR programming, you are assured
that the ISR device will not also drive those pins. This pre-
vents bus contention, and prevents the ISR devices or other
devices on the board from being damaged. ISR devices can
be programmed for the first time in-system without fear that
other board components driving the CPLD will negatively ef-
fect operation.
As previously discussed, all ISR device I/Os will initially three-
state after first power-up regardless of whether the CPLD
contains volatile or non-volatile configuration bits.
Summary
The In-System Reprogrammable feature of Cypress ISR de-
vices provides the critical capability to manipulate program-
mable device configuration without the need to desolder com-
ponents from a users board. With a good understanding of
ISR design considerations involved and adherence to the rec-
ommended layout and termination practices, a printed circuit
board designer can implement a reliable method for device
reconfiguration or in-system test using boundary scan.
The Cypress ISR PC programming cables provide the sim-
plest method to build In-System Reprogrammability of pro-
grammable devices into systems. In-System Reprogramma-
bility (ISR) of a programmable device has several benefits. It
allows engineering development and debugging to occur
without having to socket the ISR devices and without having
to remove them and reprogram them in a device programmer.
This saves time regardless of the package type used. ISR is
especially valuable when fine-pitch packages like TQFPs and
FBGAs are used. This not only saves time, it can also avoid
the high likelihood of bending leads on very fine-leaded de-
vices. Also, by allowing soldering of TQFP packages directly
onto a board without sockets, it helps to avoid spending time
simply checking device-to-socket-lead connections during
debugging. ISR also allows for designs which can be recon-
figured in the field, either by a software update or by other
input from the system. The superior routability and flexible
architecture of the Cypress ISR CPLDs enhance the value of
all of these benefits greatly by allowing design changes to be
made during prototyping, debugging, or field operation and
still successfully route to the already-defined pinout, even on
designs that utilize most or all of the devices resources.
This application note explains the available Cypress program-
ming cables and the signals they use, and also covers many
design techniques and considerations that show how to easily
use the capabilities of ISR devices. These include: descrip-
tion of the logic needed when using the dual-function pins on
applicable ISR devices, connecting ISR devices in a program-
ming chain, and ISR differences between the programmable
logic device families.
Designing a daisy-chain of ISR devices is straightforward pro-
vided that the designer follows the layout guidelines set forth
in this document. By following the recommended layout prac-
tices, board-level problems will be eliminated and a highly
reliable programming method results.
References
1. Cypress Application Note. System Design Considerations
When Using Cypress CMOS Circuits, 1993.
2. IEEE Std 1149.1-1990 Test Access Port and Boundary
Scan Architecture, IEEE Computer Society, May 1990.
3. Johnson, H. and Graham M. High-Speed Digital Design,
Prentice-Hall, Inc., 1993.
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