Cypress Semiconductor ISR 37000 CPLD Especificaciones descargar pdf (Pagina 14)

Design Considerations for ISR Programming of Cypress CPLDs

ISR*. By implementing this inversion, the inverter in Figure

14(e) can be removed, and pin B1 can be connected to pin

BE2*. The BE1*, A0, A5, B0, and B5 pin connections remain

the same.

The FCT devices shown are just one possible way of imple-

menting this logic, of course. There are others, including us-

ing extra pins and gates from an ASIC, FPGA, CPLD, or PAL

device already on the board. Regardless of whether the buffer

or multiplexer is in an FCT device, ASIC, FPGA, or other de-

vice, there will be some additional propagation delay for the

normal operating signal due to the presence of that logic. This

must be accounted for in your design. Using the

SN74CBT3384A provides the smallest extra delay, less than

one quarter of one nanosecond. The extra delay holds true

for the other cases presented next.

Dual-Function Mode Operation: I/O Pin Used as an Output

In the case of the TDI, TCK, or TMS sharing a pin with an I/O

that is used only as an output during normal operating mode,

the logic is slightly different. Much like the case above, you

can just use a pair of three-state buffers or pass-transistors to

separate the signals that are used for the two different func-

tions. In this case, however, instead of tying the two outputs

together, you tie the output of one buffer both to the dual-

function pin of the ISR device and to the input of the other

buffer. The input to the first buffer is the programming function

signal, and the output from the other buffer is the normal op-

eration output Signal. The first buffer is enabled when ISR* is

asserted and is disabled otherwise, and the second buffer is

enabled when ISR* is deasserted and is disabled otherwise.

This is shown in Figure 15. Thus, when the device is being

programmed, TDI (or TMS or TCK) is driving the TDI/IO pin

and Signal is in three-state, and when the device is not being

programmed, the TDI/IO pin is not driven as an input allowing

the ISR output to drive Signal. Because Signal is in the three-

state during programming, you may need to have a pull-up or

pull-down resistor on Signal depending on how you use it on

your board.

You can also use a SN74CBT3384A as an alternative to the

buffers, as shown in the previous case. This would be the

most flexible solution because it would work for all configura-

tions—the pin used as an I, O, or I/O—and allows you to de-

cide later exactly how to use that pin.

Dual-Function Mode Operation: I/O Pin Used as an Input and

an Output

In the case of the TDI, TCK, or TMS sharing a pin with an I/O

that really is used as a bidirectional I/O, the logic needed is a

little more complicated. As seen in Figure 16, part of the logic

is a combination of the two solutions for the two individual

cases above in the way it uses ISR* to separate the program-

ming function of TDI (or TMS or TCK) from the input and

output functions of Signal during normal operating mode.

There is more than just this logic required, however. It is also

necessary to use an extra pair of buffers to separate the input

and output functionality of Signal itself. This is required to

keep from unintentionally building a feedback loop and is im-

plemented using an extra signal that indicates the direction of

the I/O pin. In this example, we assume we have a signal

called dir, and that dir is HIGH when the I/O pin is being used

as an input and dir is LOW when the I/O pin is being used as

an output.

Figure 15. Design for Dual-Function Pins: TDI/TCK/TMS

Used as an Output

TDI

Signal

ISR*

TDI/IO

ISR

Figure 16. Design for Dual-Function Pins: TDI/TCK/TMS Used With an I/O

TDI

Signal

ISR*

TDI/I/O

ISR

dir

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