Cypress Semiconductor CY7C1381D Manual de usuario

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CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 9 of 29Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-StateWrite Cycle, Begin Burst E

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 10 of 29Truth Table for Read/Write[3,8]Function (CY7C1383D) GW BWE BWBBWAWrite Bytes D, C, A (DQD

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 11 of 29IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1381D/CY7C1383D incorporates a serial boun

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 12 of 29Bypass RegisterTo save time when serially shifting data through registers, it issometimes

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 13 of 29current instruction. When HIGH, it will enable the outputbuffers to drive the output bus.

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 14 of 293.3V TAP AC Test ConditionsInput pulse levels ...

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 15 of 29Notes: 11. All voltages referenced to VSS (GND).12. Bit #24 is “1” in the Register Defini

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 16 of 29119-Ball BGA Boundary Scan Order[13, 14]Bit # Ball ID Bit # Ball ID Bit # Ball ID Bit # B

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 17 of 29165-Ball BGA Boundary Scan Order[13, 15]Bit # Ball ID Bit # Ball ID Bit # Ball ID1N6 31D1

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 18 of 29Maximum Ratings(Above which the useful life may be impaired. For user guide-lines, not te

18-Mbit (512K x 36/1M x 18)Flow-Through SRAMCY7C1381DCY7C1383DCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 19 of 29Capacitance[19]Parameter Description Test Conditions100 TQFP Package119 BGA Package165 FB

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 20 of 29Switching Characteristics Over the Operating Range[23, 24]Parameter Description133 MHz 10

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 21 of 29Timing DiagramsRead Cycle Timing[25]Note: 25. On this diagram, when CE is LOW: CE1 is LOW

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 22 of 29 Write Cycle Timing[25, 26]Note: 26.Full width write can be initiated by either GW LOW; o

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 23 of 29Read/Write Cycle Timing[25, 27, 28]Notes: 27. The data bus (Q) remains in high-Z followin

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 24 of 29ZZ Mode Timing[29, 30]Notes: 29. Device must be deselected when entering ZZ mode. See tru

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 25 of 29Ordering InformationNot all of the speed, package and temperature ranges are available. P

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 26 of 29Package Diagrams NOTE:1. JEDEC STD REF MS-0262. BODY LENGTH DIMENSION DOES NOT INCLUDE M

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 27 of 29Package Diagrams (continued)51-85115-*B119-ball BGA (14 x 22 x 2.4 mm) (51-85115)

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 28 of 29© Cypress Semiconductor Corporation, 2006. The information contained herein is subject t

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 2 of 29 1ADDRESSREGISTERBURSTCOUNTERAND LOGICCLRQ1Q0ENABLEREGISTERSENSEAMPSOUTPUTBUFFERSINPUTREGI

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 29 of 29Document History PageDocument Title: CY7C1381D/CY7C1383D 18-Mbit (512K x 36/1M x 18) Flo

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 3 of 29Pin ConfigurationsAAAAA1A0NCNCVSSVDDAAAAAAAADQPBDQBDQBVDDQVSSQDQBDQBDQBDQBVSSQVDDQDQBDQBVS

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 4 of 29Pin Configurations (continued)2345671ABCDEFGHJKLMNPRTUVDDQNC/288MNC/144MDQPCDQCDQDDQCDQDAA

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 5 of 29Pin Configurations (continued)165-Ball FBGA Pinout (3 Chip Enable)CY7C1381D (512K x 36)234

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 6 of 29Pin DefinitionsName I/O DescriptionA0, A1, AInput-SynchronousAddress Inputs used to select

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 7 of 29Functional OverviewAll synchronous inputs pass through input registers controlledby the ri

CY7C1381DCY7C1383DDocument #: 38-05544 Rev. *E Page 8 of 29Burst SequencesThe CY7C1381D/CY7C1383D provides an on-chip two-bitwraparound burst counter