Cypress Semiconductor ISR 37000 CPLD Especificaciones descargar pdf (Pagina 12)

Design Considerations for ISR Programming of Cypress CPLDs

pins as I/Os in normal operation because their physical posi-

tion makes your board layout easier. If you want to do this in

your design, you can do it fairly easily; it simply requires a little

bit of extra logic and some additional small components. This

next section shows you how to do this.

The TDI, TCK, and TMS programming pins are all inputs to

the device during programming, and they always share pins

with bidirectional I/Os when they are dual-function pins. The

TDO programming pin, on the other hand, is an output pin

from the device during programming. It, too, always shares a

pin with a bidirectional I/O when it is a dual-function pin.

These I/O pins, in turn, can be used as input only, output only,

or bidirectional I/Os in any design, based upon the function-

ality that is described for these pins in the programmable logic

chip’s design description. The result is that there are six dif-

ferent cases to consider: An ISR input programming pin (TDI,

TCK, TMS) can share a pin with a signal that is an input, an

output, or an I/O; and you can have an ISR output program-

ming pin (TDO) sharing a pin with a signal that is an input, an

output, or an I/O. We next look at each of these six cases

individually.

What you are trying to accomplish in all of these cases is

fundamentally the same. You are trying to isolate the pro-

gramming signals from the normal operating signals on the

board. You do not want the programming signal to drive or

affect anything else on the board when you are programming

the ISR device, and you do not want the normal operating

signal to drive, affect, or be affected by the programming logic

when the ISR device is operating normally in the system. The

basic strategy in all of the cases listed above is to use three-

state buffers or multiplexers on these signals, and to have

those buffers or multiplexers controlled by the ISR* signal

from the programming cable. The ISR* signal, recall, is a sig-

nal from the programming cable that is a logic LOW when

JTAGen is enabling the ISR interface.

Dual-Function Mode Operation: I/O Pin Used as an Input

First, consider the case of the ISR programming pins that are

inputs to the device during programming; TDI, TCK, and TMS.

When one of these device pins is being used as an input

during normal operating mode, you simply have to select be-

tween one of two inputs based on whether you are in pro-

gramming mode or in operating mode. This is implemented

very easily by using a 2:1 multiplexer where ISR* is the select

line, as shown in Figure 14(a). Alternatively, you could imple-

ment this by having two three-state buffers whose inputs are

TDI (or TMS or TCK) and signal, whose outputs are tied to-

gether and to the TDI/IO pin, and whose enable lines are

controlled by opposite values of ISR*. This is shown in Figure

14(b). One way you could implement this logic is with FCT-

family devices. For example, you could use one of the four 2:1

multiplexers in a 74FCT257T to implement the logic shown in

Figure 14(a). Alternatively, you could use a pair of transceiv-

Figure 12. VHDL Code Fragment Showing pin_avoid Attribute

Figure 13. VHDL Code Fragment Showing pin_numbers Attribute

-- example of using “pin_avoid” for single–function mode of

-- dual–function devices

entity cpuctl is port (

a : in bit_vector (31 downto 0);

rd, wr : out bit;

hold : buffer bit;

status : out bit_vector (7 downto 0));

attribute pin_avoid of cpuctl:entity is “14 35 51 72 83”;

end cpuctl;

-- architecture would follow

-- example of explicit pin assignments that avoid ISR pins

-- to facilitate single–function mode of dual–function devices

entity cpuctl is port (

a : in bit_vector (15 downto 0);

rd, wr : out bit;

hold : buffer bit;

status : out bit_vector (7 downto 0));

-- assign pins below and avoid pins 14, 35, 51, 72, and 83

attribute pin_numbers of cpuctl:entity is

“a(15):12 a(14):13 a(13):15 a(12):16 a(11):17 a(10):18 a(9):19 “ &

“a(8):24 a(7):25 a(6):26 a(5):27 a(4):28 a(3):29 a(2):30 “ &

“a(1):31 a(0):33 rd:36 wr:37 hold:38 status(7):54 status(6):55 “ &

“status(5):56 status(4):57 status(3):58 status(2):59 status(1):60 “ &

“status(0):61“;

end cpuctl;

-- architecture would follow

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