Cypress Semiconductor ISR 37000 CPLD Especificaciones descargar pdf (Pagina 15)

Design Considerations for ISR Programming of Cypress CPLDs

To understand why this is necessary, consider just combining

the logic from Figure 14(b) and Figure 15. The result would

be the logic shown in Figure 17, which is different from Figure

16 in that buffers b4 and b5 were eliminated and intermediate

signals w, x, and y are now all simply connected together and

to the TDI/IO pin. In the logic of Figure 17, when the ISR

device is in normal operation mode and ISR* is HIGH, buffers

b2 and b3 would both be enabled. If Signal were an input at

that time, it would drive the input to buffer b2, whose output

would drive the input to buffer b3. The output of buffer b3

would be driving the input of b2 again, resulting in a feedback

loop that could produce undesired affects. The same thing

would happen if Signal were an output at that time.

Buffers b4 and b5 in Figure 16 prevent this. In the logic of

Figure 16, when signal is an output from the ISR device, b5

is enabled and b4 is disabled; when Signal is an input to the

device, b4 is enabled and b5 is disabled. In both cases, both

the function and value at the pin of the device and the function

and value of Signal are the same, correct, and only driven by

one source. There is no dangerous self-driving feedback sys-

tem like there is in Figure 17.

The limitation of this solution is that it requires the extra signal

dir. This signal may be already available; in fact, it may be an

input to the ISR device itself for use as the OE

-control on the

pin in question. If it is not already available, you will need to

generate it using other logic on the board. If you cannot do it

using other logic on your board, you should certainly be able

to generate it using logic inside the ISR device itself, because,

as pointed out above, it should be the same signal as the OE

used on that pin internally. To get the signal out of the ISR,

however, requires an additional pin. If you are using the logic

in Figure 16 to save a pin, having to use a pin on the device

to generate dir will not gain you anything. If generating one dir

will help you save two or three pins by allowing you to use two

or three of TDI, TCK, and TMS as dual-function pins, then you

will still have a net savings of one or two pins and it may be

worth it.

As was mentioned in the case where the TDI (or TMS or TCK)

dual-function pin was being used with an input-only pin or with

an output-only pin, you can also use the SN74CBT3384A so-

lution of Figure 14(e) when trying to use the TDI (or TMS or

TCK) dual-function pin as a bidirectional I/O pin in normal

operating mode.

The logic for using the dual-functionality of the TDO/IO pin is

essentially the same as is shown in the above three cases.

The only difference is that TDO is an output during program-

ming mode instead of an input. Therefore, the only difference

in the logic is the orientation of some of the buffers. The

solutions for the TDO case are presented without further ex-

planation. The logic diagram for the case where TDO is con-

nected to an I/O used only as an input is shown in Figure 18.

The logic diagram for the case where TDO is connected to an

I/O used only as an output is shown in Figure 19. The logic

diagram for the case where TDO is connected to an I/O really

used as a bidirectional pin is shown in Figure 20. You can

alternatively use the SN74CBT3384A solution presented in

Figure 14(e) in each of these three cases.

Figure 17. TDI/TCK/TMS Used With an I/O: Example of Incorrect Solution

TDI

Signal

ISR*

TDI/I/O

ISR

Figure 18. Design for Dual-Function Pins:

TDO Used With an Input

Figure 19. Design for Dual-Function Pins:

TDO Used With an Output

TDO

Signal

ISR*

TDO/I/O

ISR

TDO

Signal

ISR*

TDO/I/O

ISR

1 2 ... 10 11 12 13 14 15 16 17 18 19 20

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