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ZestSC1ReadSignals

ZESTSC1_STATUS ZestSC1ReadSignals( ZESTSC1_HANDLE Handle,

unsigned char *Value);

Parameters

Handle Handle of open ZestSC1 card. See ZestSC1OpenCard.

Value Pointer to location to receive active signals.

Return Value

ZESTSC1_SUCCESS Function succeeded

ZESTSC1_ILLEGAL_HANDLE Attempt to use illegal card handle

ZESTSC1_INTERNAL_ERROR An unspecified internal error occurred while

communicating with the driver

ZESTSC1_TIMEOUT Operation timed out

ZESTSC1_ILLEGAL_SIGNAL_MASK The requested mask specifies signals not

available on this card

ZESTSC1_SIGNAL_IS_OUTPUT One of the requested signals is an output and

cannot be read

Description

ZestSC1ReadSignals can be used to read the value of signals from FPGA to host. Value

is an 8 bit mask of the signal values where bit 0 is GPP0, bit 1 is GPP1, bit 2 is GPP2 and

so on. All signals of interest should be configured as FPGA to host signals by

ZestSC1SetSignalDirection.

For example:

ZESTSC1_HANDLE Handle;

unsigned long Value;

/* Open a card with ID of 1 */

ZestSC1OpenCard(1, &Handle);

/* Set GPP0 to be FPGA to host */

ZestSC1SetSignalDirecion(Handle, 0);

/* Configure the FPGA */

ZestSC1ConfigureFromFile(Handle, “example.bit”);

/* Wait for the signal to become ‘active’ */

{

ZestSC1ReadSignals(Handle, 1, &Value);

} while ((Value&1)==0);

/* Close the card */

ZestSC1CloseCard(Handle);

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Cypress Semiconductor NoBL CY7C1472V33 Guía de usuario Pagina 56