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ZestSC1SetSignalDirection

ZESTSC1_STATUS ZestSC1SetSignalDirection(ZESTSC1_HANDLE Handle,

unsigned char Direction);

Parameters

Handle Handle of open ZestSC1 card. See ZestSC1OpenCard.

Direction Mask of bits for signal direction. A 1 bit indicates a signal from

host to FPGA.

Return Value

ZESTSC1_SUCCESS Function succeeded

ZESTSC1_ILLEGAL_HANDLE Attempt to use illegal card handle

ZESTSC1_INTERNAL_ERROR An unspecified internal error occurred while

communicating with the driver

ZESTSC1_TIMEOUT Operation timed out

ZESTSC1_ILLEGAL_SIGNAL_MASK The requested mask specifies signals not

available on this card

Description

The ZestSC1 card has 8 general purpose signals routed between host and FPGA. Each of

these signals can be either a general signal from host to FPGA or from FPGA to host.

ZestSC1SetSignalDirection controls which of these functions is assigned to each of the

8 signals.

Direction is an 8 bit mask where bit 0 controls GPP0, bit 1 controls GPP1, bit 2 controls

GPP2 and so on. Each bit should be set to 1 for the signal to be host to FPGA and 0 for

the signal to be FPGA to host. Signals from host to FPGA can be controlled by calling

ZestSC1SetSignals. The host can read signals from the FPGA by calling

ZestSC1ReadSignals.

Since the 8 general purpose signals are connected to pins on the FPGA, it is important

that conflicts do not arise where both the USB interface chip and the FPGA are driving the

same wire. To prevent damage to the ZestSC1 card, it is crucial that signals set to the

host to FPGA direction (1 in the Direction bit mask) are never driven by the FPGA. Note

that all FPGA pins are tri-stated when the FPGA is unconfigured so it is safe to set the

signal direction before configuration.

For example:

ZESTSC1_HANDLE Handle;

/* Open a card with ID of 1 */

ZestSC1OpenCard(1, &Handle);

/* Set GPP0 to be host to FPGA */

ZestSC1SetSignalDirecion(Handle, 1);

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Cypress Semiconductor NoBL CY7C1472V33 Guía de usuario Pagina 52