Cypress Semiconductor CY7C1386F Manual de usuario

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CY7C1386D, CY7C1386F
CY7C1387D, CY7C1387F
18-Mbit (512 K × 36/1 M × 18) Pipelined
DCD Sync SRAM
Cypress Semiconductor Corporation 198 Champion Court San Jose, CA 95134-1709 408-943-2600
Document Number: 38-05545 Rev. *H Revised July 12, 2011
18-Mbit (512 K × 36/1 M × 18) Pi pelined DCD Sync SRAM
Features
Supports bus operation up to 250 MHz
Available speed grades are 250, 200, and 167 MHz
Registered inputs and outputs for pipelined operation
Optimal for performance (double-cycle deselect)
Depth expansion without wait state
3.3 V core power supply (V
DD
)
2.5 V or 3.3 V I/O power supply (V
DDQ)
Fast clock-to-output times
2.6 ns (for 250 MHz device)
Provides high performance 3-1-1-1 access rate
User selectable burst counter supporting Intel
Pentium
Interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
CY7C1386D/CY7C1387D available in JEDEC-standard
Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball FBGA
package. CY7C1386F/CY7C1387F available in Pb-free and
non Pb-free 119-ball BGA package
IEEE 1149.1 JTAG-compatible boundary scan
ZZ sleep mode option
Functional Description
The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F
SRAM
[1]
integrates 512 K × 36/1 M × 18 SRAM cells with
advanced synchronous peripheral circuitry and a two-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive edge triggered clock input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining chip enable (CE
1
), depth expansion
chip enables (CE
2
and
CE
3
[2]
), burst control inputs (ADSC,
ADSP
,
and
ADV), write enables (
BW
X
, and BWE), and global
write (GW). Asynchronous inputs include the output enable (OE)
and the ZZ pin.
Addresses and chip enables are registered at rising edge of
clock when either address strobe processor (ADSP
) or address
strobe controller (ADSC) are active. Subsequent burst
addresses can be internally generated as controlled by the
advance pin (ADV
).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
operations (see on page 4 and Truth Table on page 11 for further
details). Write cycles can be one to four bytes wide as controlled
by the byte write control inputs. GW
active LOW causes all bytes
to be written. This device incorporates an additional pipelined
enable register which delays turning off the output buffers an
additional cycle when a deselect is executed.This feature allows
depth expansion without penalizing system performance.
The CY7C1386D/CY7C1387D/CY7C1386F/CY7C1387F
operates from a +3.3 V core power supply while all outputs
operate with a +3.3 V or +2.5 V supply. All inputs and outputs are
JEDEC-standard and JESD8-5-compatible.
Selection Guide
Description 250 MHz 200 MHz 167 MHz Unit
Maximum access time 2.6 3.0 3.4 ns
Maximum operating current 350 300 275 mA
Maximum CMOS standby current 70 70 70 mA
Notes
1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.
2. CE
3
and CE
2
are for 100-pin TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only in Single Chip Enable.
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Indice de contenidos

Pagina 1 - DCD Sync SRAM

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387F18-Mbit (512 K × 36/1 M × 18) PipelinedDCD Sync SRAMCypress Semiconductor Corporation • 198 Champion Court • S

Pagina 2

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 10 of 36Interleaved Burst Address Table (MODE = Floating or VDD)First

Pagina 3

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 11 of 36Truth TableThe Truth Table for CY7C1386D, CY7C1386F, CY7C1387D

Pagina 4

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 12 of 36Truth Table for Read/WriteThe Truth Table for Read/Write for C

Pagina 5 - CY7C1386F (512 K × 36)

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 13 of 36IEEE 1149.1 Serial Boundary Scan (JTAG)The CY7C1386D/CY7C1387D

Pagina 6

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 14 of 36the instruction after it is shifted in, the TAP controller nee

Pagina 7

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 15 of 36TAP Controller State DiagramThe 0 or 1 next to each state repr

Pagina 8 - Single Read Accesses

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 16 of 36TAP AC Switching CharacteristicsOver the Operating RangeParame

Pagina 9 - Sleep Mode

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 17 of 363.3 V TAP AC Test ConditionsInput pulse levels ...

Pagina 10 - (MODE = Floating or V

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 18 of 36Identification Register DefinitionsInstruction FieldCY7C1386D/

Pagina 11 - CY7C1387D, CY7C1387F

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 19 of 36Boundary Scan Order119-ball BGA [17, 18]Bit # Ball ID Bit # Ba

Pagina 12

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 2 of 36Logic Block Diagram – CY7C1386D/CY7C1386F [3] (512 K × 36)Logic

Pagina 13 - TAP Instruction Set

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 20 of 36Boundary Scan Order165-ball BGA [19, 20]Bit # Ball ID Bit # Ba

Pagina 14

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 21 of 36Maximum RatingsExceeding maximum ratings may shorten the usefu

Pagina 15

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 22 of 36IDDVDD operating supply current VDD = Max., IOUT = 0 mA, f = f

Pagina 16

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 23 of 36AC Test Loads and WaveformsFigure 4. AC Test Loads and Wavefo

Pagina 17

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 24 of 36Switching CharacteristicsOver the Operating RangeParameter [24

Pagina 18

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 25 of 36Switching WaveformsFigure 5. Read Cycle Timing [30]tCYCtCLCLK

Pagina 19

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 26 of 36Figure 6. Write Cycle Timing [31]Switching Waveforms (continu

Pagina 20

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 27 of 36Figure 7. Read/Write Cycle Timing [32, 33, 34]Switching Wavef

Pagina 21

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 28 of 36Figure 8. ZZ Mode Timing [35, 36]Switching Waveforms (continu

Pagina 22

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 29 of 36Ordering InformationThe table below contains only the parts th

Pagina 23

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 3 of 36ContentsPin Configurations ...

Pagina 24

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 30 of 36Package DiagramsFigure 10: 100-pin TQFP (14 × 20 × 1.4 mm) A10

Pagina 25

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 31 of 36Figure 9. 119-ball PBGA (14 × 22 × 2.4 mm) BG119, 51-85115Pac

Pagina 26

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 32 of 36Figure 10. 165-ball FBGA (13 × 15 × 1.4 mm) BB165D/BW165D (0.

Pagina 27

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 33 of 36Acronyms Document ConventionsUnits of MeasureAcronym Descripti

Pagina 28

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 34 of 36Document History PageDocument Title: CY7C1386D/CY7C1387D/CY7C1

Pagina 29 - Ordering Code Definitions

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 35 of 36*H 3309506 OSN 07/12/2011 Updated Package Diagrams.Added Units

Pagina 30

Document Number: 38-05545 Rev. *H Revised July 12, 2011 Page 36 of 36Intel and Pentium are registered trademarks, and i486 is a trademark of Intel Co

Pagina 31

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 4 of 36Pin ConfigurationsFigure 1. 100-pin TQFP (3 Chip Enable)AAAAA1

Pagina 32

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 5 of 36Figure 2. 119-ball BGA (1 Chip Enable)Pin Configurations (cont

Pagina 33 - Units of Measure

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 6 of 36Figure 3. 165-ball FBGA (3 Chip Enable)Pin Configurations (con

Pagina 34

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 7 of 36Pin DefinitionsName I/O DescriptionA0, A1, A Input-SynchronousA

Pagina 35

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 8 of 36Functional OverviewAll synchronous inputs pass through input re

Pagina 36 - PSoC Solutions

CY7C1386D, CY7C1386FCY7C1387D, CY7C1387FDocument Number: 38-05545 Rev. *H Page 9 of 36Single Write Accesses Initiated by ADSPThis access is initiated

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