Cypress Semiconductor NoBL CY7C1472V33 Guía de usuario Pagina 11

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ZestSC1 User Guide
CONFIDENTIAL Page 11 of 57
7 Description
The block diagram of ZestSC1 is shown in Figure 3. It is a desktop board with a Xilinx
Spartan-3 FPGA with up to one million system gates. The FPGA is connected to a host
computer over High Speed USB (12 or 480Mbits/sec) for configuration and data
communication. A synchronous SRAM of either 1 or 8 MBytes stores application data, and
a 32x2 0.1” pitch header can be used for I/O.
Figure 3. ZestSC1 Block Diagram
7.1 USB
ZestSC1 is a USB device and needs to be connected to a USB host computer. It can draw
power from the USB cable or from a mains power adapter, according to the position of
J6. The USB port may be either Full speed 12Mbps (USB V1.1 or 2.0) or High speed
480Mbps (USB V2.0).
The USB controller is the Cypress EZ-USB FX2 USB Microcontroller [1]. It includes an
8051 microcontroller that is used for enumeration and board management firmware. The
8051 address and data buses are connected to the FPGA. The USB controller is
implemented entirely in hardware. The ZestSC1 comes fitted with an EEPROM containing
firmware to communicate with the supplied host driver. It is strongly recommended that
this firmware is not modified and that the supplied host driver and FPGA cores are used
for all designs. Failure to do so may result in damage to the hardware.
The main method for data communication between the FPGA and USB is by the FX2’s
FIFO interface. This can operate with its data bus 8 or 16 bits wide and at a frequency of
48MHz giving a maximum burst data rate of 96 MBytes/sec.. It is used for configuring
the FPGA from the host computer and for data communications between the FPGA and
host computer. The FX2 Serial Interface Engine SIE, which controls USB transfers, uses
USB
USB
Controller
FPGA
Spartan-3
1000
ZBT SRAM
8MBytes
49 pins of user I/O on 0.1” header
8 LEDs
16 18
49
8
Streamin
g
8 Re
g
isters
8 Fla
g
s
Interru
t
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