Cypress Semiconductor NoBL CY7C1472V33 Guía de usuario descargar pdf (Pagina 54)

Orange Tree Technologies

Page 54 of 57

ZestSC1SetSignals

ZESTSC1_STATUS ZestSC1SetSignals( ZESTSC1_HANDLE Handle,

unsigned char Value);

Parameters

Handle Handle of open ZestSC1 card. See ZestSC1OpenCard.

Value Mask of bits to set.

Return Value

ZESTSC1_SUCCESS Function succeeded

ZESTSC1_ILLEGAL_HANDLE Attempt to use illegal card handle

ZESTSC1_INTERNAL_ERROR An unspecified internal error occurred while

communicating with the driver

ZESTSC1_TIMEOUT Operation timed out

ZESTSC1_ILLEGAL_SIGNAL_MASK The requested mask specifies signals not

available on this card

ZESTSC1_SIGNAL_IS_INPUT One of the requested signals is an input and

cannot be set

Description

ZestSC1SetSignals controls the value of general purpose signals from host to FPGA.

Value is an 8 bit mask where bit 0 controls GPP0, bit 1 controls GPP1, bit 2 controls GPP2

and so on.

Each signal asserted by this function must have been set up as a host to FPGA signal by

ZestSC1SetSignalDirection prior to calling ZestSC1SetSignals.

Since the 8 general purpose signals are connected to pins on the FPGA, it is important

that conflicts do not arise where both the USB interface chip and the FPGA are driving the

same wire. To prevent damage to the ZestSC1 card, it is crucial that signals set to the

host to FPGA direction (1 in the Direction bit mask) are never driven by the FPGA. Note

that all FPGA pins are tri-stated when the FPGA is unconfigured so it is safe to set the

signal direction before configuration.

For example:

ZESTSC1_HANDLE Handle;

/* Open a card with ID of 1 */

ZestSC1OpenCard(1, &Handle);

/* Set GPP0 to be host to FPGA */

ZestSC1SetSignalDirecion(Handle, 1);

/* Configure the FPGA */

ZestSC1ConfigureFromFile(Handle, “example.bit”);

1 2 ... 49 50 51 52 53 54 55 56 57

Sin comentarios

Cypress Semiconductor NoBL CY7C1472V33 Guía de usuario Pagina 54