Cypress Semiconductor NoBL CY7C1472V33 Guía de usuario descargar pdf (Pagina 21)

ZestSC1 User Guide

CONFIDENTIAL Page 21 of 57

power switch so is available only after the FX2 has enabled the power switch using its

Port E bit 0.

The FPGA I/O banks connected to J4 are 3V3. They are NOT 5V tolerant. However 5V

signals can be connected to J4 via 180 ohm series resistors to limit the current into each

FPGA pin to less than 10mA.

As a build option, DCI reference resistors can be fitted for matching the characteristic

impedance of the IO lines for DCI buffers. The FPGA pins for the reference resistors are

the same as IO pins 2, 3, 44 & 45. Hence if the resistors are fitted then these IO pins

cannot be used for I/O. Also the FPGA pins for two of the reference resistors are the

same as pins connected to LED’s D7 and D8. Hence if the resistors are fitted then these

LED’s are removed.

7.5 LEDs

There is one LED for the FPGA configuration DONE signal, 4 LEDs indicating power supply

status, and 8 LEDs connected to the FPGA. These latter 8 LEDs are also connected to IO

signals as shown below. Figure 8 shows the positions of the LEDs.

LED Signal

1 DONE

2 IO0

3 IO1

4 IO41

5 IO42

6 IO43

7 IO44

8 IO45

9 IO46

10 5V

11 3.3V

12 Switched 3.3V

13 2.5V

LED’s 2-9 are driven active low. An LED is switched on when the IO line is low, and

requires 2mA to be drawn by the IO line for full brightness.

As a build option, DCI reference resistors can be fitted for matching the characteristic

impedance of the IO lines for DCI buffers. The FPGA pins for two of the reference

resistors are the same as pins connected to LED’s D7 and D8. Hence if the resistors are

fitted then these LED’s are removed.

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