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the FIFO interface. The FIFO interface can be controlled by either an internal master in

the FX2 or an external master in the FPGA. The internal master is a programmable state

machine called the General Programmable Interface or GPIF. Conversely, when the FIFO

interface is controlled by the FPGA it is in Slave FIFO mode.

There are also general purpose data ports connected between the FX2 and the FPGA.

These are available for general communications (flags) or for specific purposes as

described below. For more detailed descriptions of signals see [1].

FX2 Port Port signal

number

Function or Signal Name

0 FPGA configuration CS_n

1 FPGA configuration WRITE_n

2 C_PA2/SLOE – slave output enable

3 C_PA3/WU2 – 8051 wakeup

4 C_PA4/FIFOADR0 - slave FIFO address bit 0

5 C_PA5/FIFOADR1 – slave FIFO address bit 1

6 C_PA6/PKTEND – slave packet end

7 C_PA7/FLAGD/SLCS_n – slave FIFO output status flag/slave

chip select

B 0-7 FIFO interface data bits 0-7

C 0-7 General purpose bi-directional pins

D 0-7 FIFO interface data bits 8-15

0 Enable Power – active low power-on for FPGA, SRAM , etc,

which are powered off during USB enumeration

(enumeration is the USB initialisation following connection to

a computer)

1 Enable SRAM – active low chip enable for SRAM, can be

disabled to conserve power if SRAM is not used

2 VBUS monitor – monitors VBUS (5V from USB) so 8051 can

remove internal pull-up on D+ when VBUS is removed in

Full Speed mode (the pull-up is permanently removed in

High Speed mode anyway) and the board is powered from

J5 or J7

3 C_PE3

4 C_PE4

5 FPGA configuration PROG_n

6 FPGA configuration INIT_n

7 FPGA configuration DONE

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 56 57

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Cypress Semiconductor NoBL CY7C1472V33 Guía de usuario Pagina 12