Cypress Semiconductor CY7C1473BV33 Manual de usuario descargar pdf (Pagina 9)

CY7C1471BV33

CY7C1473BV33

Document Number: 001-15029 Rev. *G Page 9 of 31

simplify read/modify/write sequences, which can be reduced to

simple byte write operations.

Because the CY7C1471BV33, and CY7C1473BV33 are

common I/O devices, do not drive data into the device when the

outputs are active. The Output Enable (OE

) can be deasserted

HIGH before presenting data to the DQs and DQP

inputs. Doing

so tri-states the output drivers. As a safety precaution, DQs and

DQP

are automatically tri-stated during the data portion of a

write cycle, regardless of the state of OE

Burst Write Accesses

The CY7C1471BV33, CY7C1473BV33 have an on-chip burst

counter that enables the user to supply a single address and

conduct up to four write operations without reasserting the

address inputs. ADV/LD

must be driven LOW to load the initial

address, as described in section Single Write Accesses on page

8. When ADV/LD

is driven HIGH on the subsequent clock rise,

the chip enables (CE

, CE

, and CE

) and WE inputs are ignored

and the burst counter is incremented. Drive the correct BW

inputs in each cycle of the burst write to write the correct bytes

of data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places

the SRAM in a power conservation “sleep” mode. Two clock

cycles are required to enter into or exit from this “sleep” mode.

While in this mode, data integrity is guaranteed. Accesses

pending when entering the “sleep” mode are not considered valid

and the completion of the operation is not guaranteed. The

device must be deselected before entering the “sleep” mode.

, CE

, and CE

, must remain inactive for the duration of

ZZREC

after the ZZ input returns LOW.

Interleaved Burst Address Table

(MODE = Floating or V

)

First

Address

A1:A0

Second

Address

A1:A0

Third

Address

A1:A0

Fourth

Address

A1:A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Address Table

(MODE = GND)

First

Address

A1:A0

Second

Address

A1:A0

Third

Address

A1:A0

Fourth

Address

A1:A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min Max Unit

DDZZ

Sleep mode standby current ZZ > V

– 0.2 V – 120 mA

ZZS

Device operation to ZZ ZZ > V

– 0.2 V – 2t

CYC

ZZREC

ZZ recovery time ZZ < 0.2 V 2t

CYC

–ns

ZZI

ZZ active to sleep current This parameter is sampled – 2t

CYC

RZZI

ZZ Inactive to exit sleep current This parameter is sampled 0 – ns

1 2 3 4 5 6 7 8 9 10 11 12 13 14 ... 30 31

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