Cypress Semiconductor CY7C1473BV33 Manual de usuario descargar pdf (Pagina 17)

CY7C1471BV33

CY7C1473BV33

Document Number: 001-15029 Rev. *G Page 17 of 31

TAP AC Switching Characteristics

Over the Operating Range

Parameter

[12, 13]

Description Min Max Unit

Clock

TCYC

TCK clock cycle time 50 – ns

TCK clock frequency – 20 MHz

TCK clock HIGH time 20 – ns

TCK clock LOW time 20 – ns

Output Times

TDOV

TCK clock LOW to TDO valid – 5 ns

TDOX

TCK clock LOW to TDO invalid 0 – ns

Setup Times

TMSS

TMS setup to TCK clock rise 5 – ns

TDIS

TDI setup to TCK clock rise 5 – ns

Capture setup to TCK rise 5 – ns

Hold Times

TMSH

TMS hold after TCK clock rise 5 – ns

TDIH

TDI hold after clock rise 5 – ns

Capture hold after clock rise 5 – ns

TAP Timing

Figure 4. TAP Timing

Test Clock

(TCK)

123456

est Mode Select

(TMS)

Test Data-Out

(TDO)

CYC

Test Data-In

(TDI)

TMSH

TMSS

TDIH

TDIS

TDOX

TDOV

DON’T CARE UNDEFINED

Notes

12. t

and t

refer to the setup and hold time requirements of latching data from the boundary scan register.

13. Test conditions are specified using the load in TAP AC Test Conditions. t

= 1 ns.

1 2 ... 12 13 14 15 16 17 18 19 20 21 22 ... 30 31

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