Cypress Semiconductor CY7C1473BV33 Manual de usuario descargar pdf (Pagina 22)

CY7C1471BV33

CY7C1473BV33

Document Number: 001-15029 Rev. *G Page 22 of 31

Switching Characteristics

Over the Operating Range

Parameter

[19]

Description

133 MHz

Unit

Min Max

POWER

[20]

1–ms

Clock

CYC

Clock cycle time 7.5 – ns

Clock HIGH 2.5 – ns

Clock LOW 2.5 – ns

Output Times

CDV

Data output valid after CLK rise – 6.5 ns

DOH

Data output hold after CLK rise 2.5 – ns

CLZ

Clock to low Z

[21, 22, 23]

3.0 – ns

CHZ

Clock to high Z

[21, 22, 23]

– 3.8 ns

OEV

OE LOW to output valid – 3.0 ns

OELZ

OE LOW to output low Z

[21, 22, 23]

0–ns

OEHZ

OE HIGH to output high Z

[21, 22, 23]

– 3.0 ns

Setup Times

Address setup before CLK rise 1.5 – ns

ALS

ADV/LD setup before CLK rise 1.5 – ns

WES

WE, BW

setup before CLK rise 1.5 – ns

CENS

CEN

setup before CLK rise

1.5 – ns

Data input setup before CLK rise 1.5 – ns

CES

Chip enable setup before CLK rise 1.5 – ns

Hold Times

Address hold after CLK rise 0.5 – ns

ALH

ADV/LD hold after CLK rise 0.5 – ns

WEH

WE, BW

hold after CLK rise 0.5 – ns

CENH

CEN hold after CLK rise 0.5 – ns

Data input hold after CLK rise 0.5 – ns

CEH

Chip enable hold after CLK rise 0.5 – ns

Notes

19. Unless otherwise noted in the following table, timing reference level is 1.5 V when V

DDQ

= 3.3 V and is 1.25 V when V

DDQ

= 2.5 V. Test conditions shown in part (a)

of Figure 5 on page 21 unless otherwise noted.

20. This part has an internal voltage regulator; t

POWER

is the time that the power must be supplied above V

DD(minimum)

initially, before a read or write operation is initiated.

21. t

CHZ

, t

CLZ

OELZ

, and t

OEHZ

are specified with AC test conditions shown in part (b) of Figure 5 on page 21. Transition is measured ±200 mV from steady-state voltage.

22. At any supplied voltage and temperature, t

OEHZ

is less than t

OELZ

and t

CHZ

is less than t

CLZ

to eliminate bus contention between SRAMs when sharing the same

data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to

achieve High Z before Low Z under the same system conditions.

23. This parameter is sampled and not 100% tested.

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