Cypress Semiconductor CYV15G0404DXB Guía de usuario descargar pdf (Pagina 28)

CYV15G0404DXB Evaluation Board

Users Guide

Page 28 of 56

7.3.2 Test Equipment Set-up

Figure 7-2 shows the test equipment set-up for BIST on channel A and reclocker mode for channel B.

7.3.3 Test Set-up

The intention of this set-up is to test the CYV15G0404DXB in reclocker mode. For this test, channel A will transmit BIST data

which will be received by channel B. Channel B will reclock the data and retransmit it to channel A. Follow the procedure below

for the test set-up.

1. Connect a SMA cable from one output of the pulse generator to the REFCLKA+ input. Connect a SMA cable from the other

output of the pulse generator to the REFCLKB+ input. Set the frequency of the pulse generator to 125 MHz. This test is using

the Single-ended SMA clock option (see Section 6.4 on page 18).

2. Connect two SMA cables from SEROUTA+ to SERINB+ and from SEROUTA- to SERINB-. Connect two more SMA cables

from SEROUTB+ to SERINA+ and from SEROUTB- to SERINA-.

3. Adjust the power supply to 3.3V and 3A limit. Apply power to the board and chip by connecting 3.3V banana plugs to J48 and

J50. Connect a banana plug from ground on the power supply to J49.

4. Verify that the power supply LEDs (D6 and DT6) are on.

5. Set SPDSELA and SPDSELB to HIGH (see Figure 6-1 on page 17).

6. Set LPEN[A..B](S2) to LOW, ULC[A..B]

(S3) to HIGH, and INSEL[A..B] to HIGH. Set RCLKENA(S7) to LOW, and RCLK-

ENB(S7) to HIGH.

7. Make sure the jumpers for WREN

(J39) and RESET(J40) are configured to enable the push buttons (see Figure 6-3 on page

17).

8. Press and release RESET

to reset the board.

9. Verify that all LFIx

LEDs are ON, indicating line faults on all channels.

10.Configure the control signals for channels A and B according to the configuration table below (refer to Section 6.3 on page

17). Note that for channel B, only address 5 needs to be configured.

3.3V 3.0A

Power Supply

3.3V GND

3.3V

GND

Oscilloscope

Input

SEROUTA1

RXSTA[2:1]

Evaluation Board

CYV15G0404DXB

Figure 7-10. Pictorial Representation of the Reclocker Test Equipment Set-up

Pulse Generator

Output

REFCLKA

Vcc

SERINB1

SEROUTB1

SERINA1

Output

REFCLKB

3.3V

[+] Feedback

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