Cypress Semiconductor CYV15G0404DXB Guía de usuario descargar pdf (Pagina 13)

CYV15G0404DXB Evaluation Board

Users Guide

Page 13 of 56

Figure 5-3 shows the optical interface connector J25, along with the signal name for each pin. For a description of each signal,

refer to the Small-form Factor Pluggable (SFP) Transceiver Multi-source agreement (MSA). Figure 5-4 shows the JTAG interface

connector and the signal names for each pin. For a description of each signal, consult the CYV15G0404DXB data sheet.

Figure 5-4 also shows the control pin header JTAG RESET (J41). It is described in Table 5-2.

Table 5-2 provides a brief description of all the control pins from J31 to J41.

The SPDSELX signals are 3-level inputs. This means that they operate at three voltage levels, termed as:

• HIGH (Direct connection to V

)

• MID (Open)

• LOW (Direct connection to V

, i.e., GND).

Power

D6 Power Indicator Indicates if the power supply is ON. The LED glows when the power supply is ON.

J48 3.3V Banana Jack Connector for power supply to the board

• +3.3 V DC

DT6 Power Indicator Indicates if the power supply is ON. The LED glows when the power supply is ON.

J50 V

Banana Jack Connector for power supply to the chip

• +3.3 V DC

J49 GND Banana Jack

• Ground

Switches

S1 ADDR[3:0] Configuration Addressing Bus Dip Switches

S2 LPENx Loop Enable Dip Switch for channel x

S3 ULCx

INSELx

Use Local Clock Dip Switch for channel x

Receive Input Selector Dip Switch for channel x

S4 DATA[7:0] Configuration Data Bus Dip Switches

S5 WREN

Control Write Enable Push-Button Switch (Active LOW)

S6 RESET Asynchronous Device Reset (Active LOW)

S7 RCLKENx Reclocker Enable for channel x

JTAG JTAG Interface Standard JTAG Interface. CYV15G0404DXB does not have a dedicated JTAG

reset. It has a built-in power-on-reset circuit for resetting the JTAG logic.

Table 5-1. Description of Connectors of the CYV15G0404DXB Evaluation Board (continued)

Connectors Signals Description

Figure 5-3. Optical Interface Signals

OPT_RATE_SEL

OPT_TX_DISABLE

OPT_TX_FAULT_A

OPT_TX_FAULT_B

OPT_TX_FAULT_C

OPT_TX_FAULT_D

OPT_LOS_A

OPT_LOS_B

OPT_LOS_C

OPT_LOS_D

No Connection

GND

VCC

Figure 5-4. JTAG Interface Signals

TMS

TCK

TDI

TRST

GND

No Connection

VCC

TDO

JTAG

RESET(J41)

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Cypress Semiconductor CYV15G0404DXB Guía de usuario Pagina 13

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