Cypress Semiconductor CYV15G0404DXB Guía de usuario descargar pdf (Pagina 19)

CYV15G0404DXB Evaluation Board

Users Guide

Page 19 of 56

7.0 Test Modes

The different test modes discussed in this document are BIST, parallel data, and reclocker test modes, including independent

clocking on multiple channels.

BIST Mode

CYV15G0404DXB has the Built-In Self-Test (BIST) capability. Each transmit and receive channel contains an independent BIST

Pattern Generator and Checker. This BIST hardware allows at-speed testing of the high-speed serial data paths in each transmit

and receive section, and across the interconnecting links.

Figure 7-1 shows the two BIST modes of operation: External loopback BIST mode and Internal loopback BIST mode.

To switch between BIST modes, use the LPENx DIP switch. LPENx = HIGH for Internal and LPENx = LOW for External BIST

mode for channel x. For external BIST mode, connect two SMA-to-SMA cables from SEROUTx1+ to SERINx1+ and from

SEROUTx1- to SERINx1-. For internal BIST mode, no cables are required. An example of external BIST mode is described in

Section 7.1.1.4 on page 21.

Two examples of BIST will be described in the sections.

• Single Channel BIST

• Four Channel BIST

Parallel Data Test Mode

The variations discussed in this document for this mode are

• Parallel-in — parallel-out mode (Encoder Enabled) at two different frequencies

• Parallel-in — parallel-out mode (Encoder Bypassed)

• Parallel-in — serial-out mode (testing the transmit side).

The detailed description of each test will comprise

• Equipment required (equipment, cable etc.)

• Test set-up

• Result verification

• Operational variations

7.1 BIST Test Set-up

7.1.1 Single Channel BIST Set-up

7.1.1.1 Equipment Required

Equipment needed:

• CYV15G0404DXB evaluation board

• Instrument grade power supply 3-amp current limit @ 3.3V

• Oscilloscope (500 MHz or better).

Optional Equipment:

• Digital signal analyzer (to observe eye diagrams)

• Pulse generator (20–150 MHz)

TX BIST LFSR

RX BIST LFSR

Parallel Inputs Ignored

Ext. BIST

Figure 7-1. BIST Mode Operation

Int. BIST

OUTx±

INx±

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