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Cypress Semiconductor CYV15G0404DXB Guía de usuario Pagina 21

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CYV15G0404DXB Evaluation Board
Users Guide
Page 21 of 56
Steps 10 through 12 are for result verification of the BIST on channel A:
10.Verify that the LFIA
LED turns off.
11.Connect a probe from the oscilloscope to RXSTA1 and verify that RXSTA1 signal has pulses of approximately 8.0-ns (1/125.0
MHz) width and 4.2-µs (8.0 ns/character * 527 characters/BIST sequence) period.
12.Verify that RXSTA2 remains low to indicate that there are no BIST errors.
Optional: Check the BIST serial out data as an eye diagram by following the procedure below.
13.Change LPENA (S2) to LOW. Notice that the LFIA
LED will turn ON.
14.Connect a pair of serial outputs (SEROUTA1+/SEROUTA1-) to the digital signal analyzer using SMA cables.
15.Trigger the analyzer by connecting an SMA-to-SMA cable from TXCLKOA (J10) to the trigger input of the analyzer.
16.Verify on the analyzer that the eye diagram looks as shown in Figure 7-3. Make sure that the eye-width is 1-bit period.
Note: This test can be repeated for other channels by changing the configuration of the associated bits for each channel.
7.1.1.4 External Loopback Mode
Electrical Transmission
For external loopback, connect SMA-to-SMA cables from SEROUTA1+ (J16A) to SERINA1+ (J13A) and from SEROUTA1-
(J15A) to SERINA1- (J14A). See Figure 7-4. Also, the control signals for Loop Enable, Use Local Clock and Input Select need
to be configured (see Figure 7-5). Set LPENA = LOW for external loopback mode, set ULCA
= HIGH for clock and data recovery,
and set RCLKENA = LOW to disable the reclocker function. Lastly, set INSELA = HIGH to select the SERINA1 SMA connectors.
To run an external loopback BIST test, repeat the procedure in Section 7.1.1.3 on page 20, but replace the values for LPENA,
ULCA
, RCLKENA, and INSELA in Step 5 with the values listed in this section.
Table 7-1. Device Control Latch Configuration for BIST on Channel A
ADDR Chnl Type DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Reset Value
0
(0000b)
AS
RFMODE
A[1] = ‘1’
RFMODE
A[0] =’0
FRAMCHAR
A = ‘1’
DECMODE
A = ‘1’
DECBYP
A = ‘1’
RXCKSEL
A = ‘1’
RXRATE
A = ‘1’
GLEN0
= ‘1’
10111111
1
(0001b)
AS
SDASEL2
A[1] = ‘1’
SDASEL2
A[0] = ‘0’
SDASEL1
A[1] = ‘1’
SDASEL1
A[0] = ‘0’
ENCBYP
A = ‘1’
TXCKSEL
A = ‘1’
TXRATE
A =’0’
GLEN1
= ‘1’
10101101
2
(0010b)
AD
RFEN
A = ‘1’
RXPLLPD
A = ‘1’
RXBIST
A = ‘0’
TXBIST
A = ‘0’
OE2
A = ‘1’
OE1
A = ‘1’
PABRST
A = ‘0’
GLEN2
= ‘1’
10110011
Figure 7-3. The Eye Diagram through the Signal Analyzer
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