Cypress Semiconductor CY7B9911V Manual de usuario

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High-Speed Low-Voltage Programmable
Skew Clock Buffer (LV-PSCB)
CY7B9911
V
3.3V RoboClock+™
Cypress Semiconductor Corporation 3901 North First Street San Jose, CA 95134 408-943-2600
Document #: 38-07408 Rev. *B Revised December 13, 2004
Features
All output pair skew <100 ps typical (250 max.)
3.75- to 110-MHz output operation
User-selectable output functions
Selectable skew to 18 ns
Inverted and non-inverted
Operation at
1
2
and
1
4
input frequency
Operation at 2x and 4x input frequency (input as low
as 3.75 MHz)
Zero input-to-output delay
50% duty-cycle outputs
LVTTL outputs drive 50 terminated lines
Operates from a single 3.3V supply
Low operating current
32-pin PLCC package
Jitter 100 ps (typical)
Functional Description
The CY7B9911V 3.3V RoboClock+™ High-Speed Low-
Voltage Programmable Skew Clock Buffer (LVPSCB) offers
user-selectable control over system clock functions. These
multiple-output clock drivers provide the system integrator with
functions necessary to optimize the timing of high-perfor-
mance computer systems. Eight individual drivers, arranged
as four pairs of user-controllable outputs, can each drive termi-
nated transmission lines with impedances as low as 50 while
delivering minimal and specified output skews and full-swing logic
levels (LVTTL).
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are deter-
mined by the operating frequency with outputs able to skew up
to ±6 time units from their nominal “zero” skew position. The
completely integrated PLL allows external load and trans-
mission line delay effects to be canceled. When this “zero
delay” capability of the LVPSCB is combined with the
selectable output skew functions, the user can create
output-to-output delays of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi-
plied by two or four at the clock destination. This facility
minimizes clock distribution difficulty while allowing maximum
system clock speed and flexibility.
Logic Block Diagram Pin Configuration
TEST
FB
REF
VCO AND
TIME UNIT
GENERATOR
FS
SELECT
INPUTS
(THREE
LEVEL)
SKEW
SELECT
MATRIX
1234323130
17161514 18 19 20
5
6
7
8
9
10
11
12
13
29
28
27
26
25
24
23
22
21
3F0
FS
V
REF
GND
TEST
2F1
FB
2Q1
2Q0
4F0
4F1
3F0
3F1
2F0
2F1
1F0
1F1
4Q0
4Q1
3Q0
3Q1
2Q0
2Q1
1Q0
1Q1
CCQ
2F0
GND
1F1
1F0
V
CCN
1Q0
1Q1
GND
GND
3Q1
3Q0
CCN
V
CCN
V
3F1
4F0
4F1
V
CCQ
V
CCN
4Q1
4Q0
GND
GND
PLCC
CY7B9911V
FILTER
PHASE
FREQ
DET
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Indice de contenidos

Pagina 1 - Skew Clock Buffer (LV-PSCB)

High-Speed Low-Voltage ProgrammableSkew Clock Buffer (LV-PSCB)CY7B9911V3.3V RoboClock+™Cypress Semiconductor Corporation • 3901 North First Street •

Pagina 2

CY7B9911V3.3V RoboClock+™Document #: 38-07408 Rev. *B Page 10 of 12 AC Timing DiagramsOrdering InformationAccuracy (ps) Ordering Code Package TypeOp

Pagina 3

CY7B9911V3.3V RoboClock+™Document #: 38-07408 Rev. *B Page 11 of 12© Cypress Semiconductor Corporation, 2004. The information contained herein is su

Pagina 4

CY7B9911V3.3V RoboClock+™Document #: 38-07408 Rev. *B Page 12 of 12Document History PageDocument Title: CY7B9911V 3.3V RoboClock+ High-Speed Low-Vol

Pagina 5

CY7B9911V3.3V RoboClock+™Document #: 38-07408 Rev. *B Page 2 of 12Block Diagram DescriptionPhase Frequency Detector and FilterThese two blocks accep

Pagina 6

CY7B9911V3.3V RoboClock+™Document #: 38-07408 Rev. *B Page 3 of 12Test ModeThe TEST input is a three-level input. In normal systemoperation, this pi

Pagina 7

CY7B9911V3.3V RoboClock+™Document #: 38-07408 Rev. *B Page 4 of 12Operational Mode DescriptionsFigure 2 shows the LVPSCB configured as a zero-skew c

Pagina 8

CY7B9911V3.3V RoboClock+™Document #: 38-07408 Rev. *B Page 5 of 12skews to +6 tU, a total of +10 tU skew is realized.) Many other config-urations ca

Pagina 9

CY7B9911V3.3V RoboClock+™Document #: 38-07408 Rev. *B Page 6 of 12Figure 8 shows the CY7B9911V connected in series toconstruct a zero-skew clock dis

Pagina 10 - 3.3V RoboClock+™

CY7B9911V3.3V RoboClock+™Document #: 38-07408 Rev. *B Page 7 of 12Maximum Ratings(Above which the useful life may be impaired. For user guide-lines,

Pagina 11

CY7B9911V3.3V RoboClock+™Document #: 38-07408 Rev. *B Page 8 of 12Capacitance[10]Parameter Description Test Conditions Max. UnitCINInput Capacitance

Pagina 12

CY7B9911V3.3V RoboClock+™Document #: 38-07408 Rev. *B Page 9 of 12tJRCycle-to-Cycle Output JitterRMS[12]25 psPeak-to-Peak[12]200 psSwitching Charact

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