Cypress Semiconductor CYV15G0404DXB Guía de usuario descargar pdf (Pagina 15)

CYV15G0404DXB Evaluation Board

Users Guide

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RXCKSELx Receive Clock Select

• When 1, the associated Output Registers are clocked by REFCLKx

• When 0, the associated Output Registers are clocked by the recovered byte clock

RXRATEx Receive Clock Rate Select.

• When 1, RXCLK output for channel x is half the character rate

• When 0, RXCLK output for channel x is the full character rate

When RXCKSELx = 1 and REFCLKx± is a half-rate clock, RXRATEx isn’t interpreted and the

RXCLKx± clock outputs follow the reference clock operating at half the character rate.

SDASEL1x[1:0] Primary Serial Data Input Signal Detector Amplitude Select.

• When SDASEL1x[1:0] = 00, the Analog Signal Detector is disabled

• When SDASEL1x[1:0]= 01, the peak-peak differential voltage threshold level is 140 mv

• When SDASEL1x[1:0]= 10, the peak-peak differential voltage threshold level is 280 mv

• When SDASEL1x[1:0]= 11, the peak-peak differential voltage threshold level is 420 mv

SDASEL2x Secondary Serial Data Input Signal Detector Amplitude Select.

• When SDASEL2x[1:0] = 00, the Analog Signal Detector is disabled

• When SDASEL2x[1:0]= 01, the peak-peak differential voltage threshold level is 140 mv

• When SDASEL2x[1:0]= 10, the peak-peak differential voltage threshold level is 280 mv

• When SDASEL2x[1:0]= 11, the peak-peak differential voltage threshold level is 420 mv

ENCBYPx Transmit Encoder Bypass

• When 1, the encoder is enabled

• When 0, the encoder is bypassed and raw 10-bit characters are transmitted

TXCKSELx Transmit Clock Select

• When 1, the associated Input Registers are clocked by REFCLKx

• When 0, the associated Input Registers are clocked by the TXCLKx input

TXRATEx Transmit PLL Clock Rate Select

• When 1, the transmit PLL multiplies REFCLKx by 20 to generate the bit-rate clock

• When 0, the transmit PLL multiplies REFCLKx by 10 to generate the bit-rate clock

RFENx Reframe Enable

• When 1, the framer is enabled

• When 0, the framer is disabled

RXPLLPDx Receive Channel Enable

• When 1, the PLL and analog circuitry are enabled

• When 0, the PLL and analog circuitry are disabled

RXBISTx Receive BIST Disable

• When 1, the receiver BIST function is disabled

• When 0, the receiver BIST function is enabled

TXBISTx Transmit BIST Disable

• When 1, the transmitter BIST function is disabled

• When 0, the transmitter BIST function is enabled

OE2x Secondary Differential Serial Data Output Driver Enable

• When 1, the output driver is enabled allowing data to be transmitted

• When 0, the output driver is disabled

Table 5-3. Device Control Latch Description (continued)

Pin Name Characteristics

[+] Feedback

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 56 57

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