Cypress Semiconductor CY7C1386F Manual de usuario descargar pdf (Pagina 7)

CY7C1386D, CY7C1386F

CY7C1387D, CY7C1387F

Document Number: 38-05545 Rev. *H Page 7 of 36

Pin Definitions

Name I/O Description

, A

, A Input-

Synchronous

Address inputs used to select one of the address locations. Sampled at the rising edge of the CLK

if ADSP

or ADSC is active LOW, and CE

, and

[4]

are sampled active. A1: A0 are fed to the

two-bit counter.

, BW

Input-

Synchronous

Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled

on the rising edge of CLK.

GW Input-

Synchronous

Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a global write

is conducted (all bytes are written, regardless of the values on BW

and BWE).

BWE

Input-

Synchronous

Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted

LOW to conduct a byte write.

CLK Input-

Clock

Clock input. Used to capture all synchronous inputs to the device. Also used to increment the burst

counter when ADV

is asserted LOW, during a burst operation.

Input-

Synchronous

Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE

[4]

to select or deselect the device. ADSP is ignored if CE

is HIGH. CE

is sampled only when

a new external address is loaded.

[4]

Input-

Synchronous

Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE

and CE

[4]

to select or deselect the device. CE

is sampled only when a new external address is loaded.

[4]

Input-

Synchronous

Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE

and

to select or deselect the device. Not connected for BGA. Where referenced, CE

[4]

is assumed

active throughout this document for BGA. CE

is sampled only when a new external address is loaded.

Input-

Asynchronous

Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW,

the I/O pins behave as outputs. When deasserted HIGH, DQ pins are tristated, and act as input data

pins. OE

is masked during the first clock of a read cycle when emerging from a deselected state.

ADV

Input-

Synchronous

Advance input signal, sampled on the rising edge of CLK, active LOW. When asserted, it

automatically increments the address in a burst cycle.

ADSP Input-

Synchronous

Address strobe from processor, sampled on the rising edge of CLK, active LOW. When asserted

LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded

into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is

ignored when CE

is deasserted HIGH.

ADSC

Input-

Synchronous

Address strobe from controller, sampled on the rising edge of CLK, active LOW. When asserted

LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded

into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.

ZZ Input-

Asynchronous

ZZ sleep input, active HIGH. When asserted HIGH places the device in a non-time critical sleep

condition with data integrity preserved. For normal operation, this pin has to be LOW. ZZ pin has an

internal pull down.

DQs,

DQP

I/O-

Synchronous

Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the

rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the

addresses presented during the previous

clock rise of the read

cycle. The direction of the pins is

controlled by OE

. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQP

are placed in a tristate condition.

Power Supply Power supply inputs to the core of the device.

Ground Ground for the core of the device.

SSQ

I/O Ground Ground for the I/O circuitry.

DDQ

I/O Power

Supply

Power supply for the I/O circuitry.

Note

4. CE

and CE

are for 100-pin TQFP and 165-ball FBGA packages only. 119-ball BGA is offered only in Single Chip Enable.

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