Cypress Semiconductor CY7C1386F Manual de usuario descargar pdf (Pagina 15)

CY7C1386D, CY7C1386F

CY7C1387D, CY7C1387F

Document Number: 38-05545 Rev. *H Page 15 of 36

TAP Controller State Diagram

The 0 or 1 next to each state represents the value of TMS at the

rising edge of TCK.

TAP Controller Block Diagram

TAP Timing Diagram

TEST-LOGIC

RESET

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-DR

CAPTURE-IR

SHIFT-IR

EXIT1-DR

PAUSE-DR

EXIT1-IR

PAUSE-IR

EXIT2-DR

UPDATE-DR

EXIT2-IR

UPDATE-IR

1 1

0 0

1 1

0 0

1 0

Bypass Register

Instruction Register

012

Identiﬁcation Register

012293031 ...

Boundary Scan Register

012..x ...

election

Circuitr

Selection

Circuitry

TCK

TMS

TAP CONTROLLER

TDI TDO

Test Clock

(TCK)

123456

Test Mode Select

(TMS)

Test Data-Out

(TDO)

CYC

Test Data-In

(TDI)

TMSH

TMSS

TDIH

TDIS

TDOX

TDOV

DON’T CARE UNDEFINED

[+] Feedback

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 35 36

DCD Sync SRAM 1
CY7C1387F (1 M × 18) 5
CY7C1386F (512 K × 36) 5
Single Read Accesses 8
Burst Sequences 9
Sleep Mode 9
(MODE = Floating or V 10
CY7C1386D, CY7C1386F 11
CY7C1387D, CY7C1387F 11
Disabling the JTAG Feature 13
Test Access Port (TAP) 13
Performing a TAP Reset 13
TAP Registers 13
TAP Instruction Set 13
Ordering Code Definitions 29
Units of Measure 33
Products 36
PSoC Solutions 36

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