Document Number : 38-16007 Rev. *L Page 16 of 34
Note
6. All status bits are set and readable in the registers regardless of IRQ enable status. This allows a polling scheme to be implemented without enabling IRQs. The
status bits are affected by the TX Enable and RX Enable (Reg 0x03, bits 7:6). For example, the transmit status will read 0 if the IC is not in transmit mode. These
registers are read-only.
Table 15. Transmit SERDES Interrupt Status
[6]
Addr: 0x0E REG_TX_INT_STAT Default: 0x00
76543210
Reserved Underflow Overflow Done Empty
Bit Name Description
7:4 Reserved These bits are reserved. This register is read-only.
3 Underflow The Underflow bit is used to signal when an underflow condition associated with the Transmit SERDES Data register
(Reg 0x0F) has occurred.
1 = Underflow Interrupt pending.
0 = No Underflow Interrupt pending.
This IRQ will assert during an underflow condition to the Transmit SERDES Data register (Reg 0x0F). An underflow
occurs when the transmitter is ready to sample transmit data, but there is no data ready in the Transmit SERDES
Data register (Reg 0x0F). This will only assert after the transmitter has transmitted at least one bit. This bit is cleared
by reading the Transmit Interrupt Status register (Reg 0x0E).
2 Overflow The Overflow bit is used to signal when an overflow condition associated with the Transmit SERDES Data register
(0x0F) has occurred.
1 = Overflow Interrupt pending.
0 = No Overflow Interrupt pending.
This IRQ will assert during an overflow condition to the Transmit SERDES Data register (Reg 0x0F). An overflow
occurs when the new data is loaded into the Transmit SERDES Data register (Reg 0x0F) before the previous data
has been sent. This bit is cleared by reading the Transmit Interrupt Status register (Reg 0x0E).
1 Done The Done bit is used to signal the end of a data transmission.
1 = Done Interrupt pending.
0 = No Done Interrupt pending.
This IRQ will assert when the data is finished sending a byte of data and there is no more data to be sent. This will
only assert after the transmitter has transmitted as least one bit. This bit is cleared by reading the Transmit Interrupt
Status register (Reg 0x0E)
0 Empty The Empty bit is used to signal when the Transmit SERDES Data register (Reg 0x0F) has been emptied.
1 = Empty Interrupt pending.
0 = No Empty Interrupt pending.
This IRQ will assert when the transmit serdes is empty. When this IRQ is asserted it is ok to write to the Transmit
SERDES Data register (Reg 0x0F). Writing the Transmit SERDES Data register (Reg 0x0F) will clear this IRQ. It
will be set when the data is loaded into the transmitter, and it is ok to write new data.
Not Recommended for New Designs
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