
Document #: 38-05486 Rev. *H Page 11 of 16
Note
25. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on this pin is not permitted.
Truth Table
CE
[25]
WE OE BHE BLE Inputs/Outputs Mode Power
H X X X X High Z Deselect/power down Standby (I
SB
)
L X X H H High Z Output disabled Active (I
CC
)
L H L L L Data out (I/O
0
–I/O
15
)Read Active (I
CC
)
L H L H L Data out (I/O
0
–I/O
7
);
I/O
8
–I/O
15
in High Z
Read Active (I
CC
)
L H L L H Data out (I/O
8
–I/O
15
);
I/O
0
–I/O
7
in High Z
Read Active (I
CC
)
L H H L L High Z Output disabled Active (I
CC
)
L H H H L High Z Output disabled Active (I
CC
)
L H H L H High Z Output disabled Active (I
CC
)
L L X L L Data in (I/O
0
–I/O
15
) Write Active (I
CC
)
L L X H L Data in (I/O
0
–I/O
7
);
I/O
8
–I/O
15
in High Z
Write Active (I
CC
)
L L X L H Data in (I/O
8
–I/O
15
);
I/O
0
–I/O
7
in High Z
Write Active (I
CC
)
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