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Cypress Semiconductor MoBL CY62126EV30 Manual de usuario

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CY62126EV30 MoBL
1-Mbit (64K x 16) Static RAM
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05486 Rev. *H Revised December 17, 2010
Features
■ High speed: 45 ns
■ Temperature ranges
❐ Industrial: –40 °C to +85 °C
❐ Automotive: –40 °C to +125 °C
■ Wide voltage range: 2.2 V to 3.6 V
■ Pin compatible with CY62126DV30
■ Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 4 A
■ Ultra low active power
❐ Typical active current: 1.3 mA at f = 1 MHz
■ Easy memory expansion with CE and OE features
■ Automatic power down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Offered in Pb-free 48-ball very fine pitch ball grid array (VFBGA)
and 44-pin thin small outline package (TSOP) II packages
Functional Description
The CY62126EV30 is a high performance CMOS static RAM
organized as 64K words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life(MoBL
®
) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption when addresses are not toggling. Placing the
device in standby mode reduces power consumption by more
than 99 percent when deselected (CE
HIGH). The input and
output pins (I/O
0
through I/O
15
) are placed in a high impedance
state when the device is deselected (CE
HIGH), the outputs are
disabled (OE
HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE
, BLE HIGH) or during a write
operation (CE
LOW and WE LOW).
To write to the device, take Chip Enable (CE
) and Write Enable
(WE
) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O
0
through I/O
7
) is written into the location
specified on the address pins (A
0
through A
15
). If Byte High
Enable (BHE
) is LOW, then data from I/O pins (I/O
8
through
I/O
15
) is written into the location specified on the address pins
(A
0
through A
15
).
To read from the device, take Chip Enable (CE
) and Output
Enable (OE
) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE
) is LOW, then data from the memory
location specified by the address pins appear on I/O
0
to I/O
7
. If
Byte High Enable (BHE
) is LOW, then data from memory
appears on I/O
8
to I/O
15
. See the “Truth Table” on page 11 for a
complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
64K x 16
RAM Array
I/O
0
–I/O
7
ROW DECODER
A
8
A
7
A
6
A
5
A
2
COLUMN DECODER
A
11
A
12
A
13
A
14
A
15
SENSE AMPS
DATA IN DRIVERS
OE
A
4
A
3
I/O
8
–I/O
15
CE
WE
BHE
A
0
A
1
A
9
A
10
BLE
Logic Block Diagram
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Indice de contenidos

Pagina 1 - 1-Mbit (64K x 16) Static RAM

CY62126EV30 MoBL1-Mbit (64K x 16) Static RAMCypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600Document

Pagina 2

CY62126EV30 MoBLDocument #: 38-05486 Rev. *H Page 10 of 16Figure 9. Write Cycle No. 3 (WE controlled, OE LOW [23]Figure 10. Write Cycle No. 4 (BH

Pagina 3

CY62126EV30 MoBLDocument #: 38-05486 Rev. *H Page 11 of 16Note25. Chip enable must be at CMOS levels (not floating). Intermediate voltage levels on

Pagina 4

CY62126EV30 MoBLDocument #: 38-05486 Rev. *H Page 12 of 16Ordering Code DefinitionsOrdering InformationSpeed(ns) Ordering CodePackageDiagramPackage

Pagina 5

CY62126EV30 MoBLDocument #: 38-05486 Rev. *H Page 13 of 16Package DiagramsFigure 11. 48-Ball VFBGA (6 x 8 x 1 mm), 51-8515051-85150 *F

Pagina 6

CY62126EV30 MoBLDocument #: 38-05486 Rev. *H Page 14 of 16Figure 12. 44-Pin TSOP II, 51-85087AcronymsMAXMIN.DIMENSION IN MM (INCH)(OPTIONAL)CAN BE

Pagina 7

CY62126EV30 MoBLDocument #: 38-05486 Rev. *H Page 15 of 16Document History PageDocument Title: CY62126EV30 MoBL®, 1-Mbit (64K x 16) Static RAMDocum

Pagina 8

Document #: 38-05486 Rev. *H Revised December 17, 2010 Page 16 of 16MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress

Pagina 9

CY62126EV30 MoBLDocument #: 38-05486 Rev. *H Page 2 of 16ContentsPin Configuration ... 3M

Pagina 10 - CY62126EV30 MoBL

CY62126EV30 MoBLDocument #: 38-05486 Rev. *H Page 3 of 16Pin ConfigurationFigure 1. 48-Ball VFBGA (Top View) Figure 2. 44-Pin TSOP II (Top View)

Pagina 11

CY62126EV30 MoBLDocument #: 38-05486 Rev. *H Page 4 of 16Maximum RatingsExceeding maximum ratings may shorten the battery life of the device. These

Pagina 12

CY62126EV30 MoBLDocument #: 38-05486 Rev. *H Page 5 of 16Capacitance For all packages. Tested initially and after any design or process changes tha

Pagina 13

CY62126EV30 MoBLDocument #: 38-05486 Rev. *H Page 6 of 16Notes8. Typical values are included for reference only and are not guaranteed or tested. T

Pagina 14

CY62126EV30 MoBLDocument #: 38-05486 Rev. *H Page 7 of 16Switching Characteristics Over the Operating Range[11, 12]Parameter Description45 ns (Indu

Pagina 15

CY62126EV30 MoBLDocument #: 38-05486 Rev. *H Page 8 of 16Switching WaveformsFigure 5. Read Cycle No. 1(Address transition controlled)[16, 17]Figur

Pagina 16

CY62126EV30 MoBLDocument #: 38-05486 Rev. *H Page 9 of 16Figure 7. Write Cycle No. 1 (WE controlled)[19, 20, 21]Figure 8. Write Cycle No. 2 (CE c

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