Cypress Semiconductor CY8C24894 Especificaciones descargar pdf (Pagina 35)

CY8C24894

Document Number: 001-53754 Rev. *F Page 35 of 50

Packaging Information

This section illustrates the package specification for the CY8C24x94 PSoC devices, along with the thermal impedance for the package

and solder reflow peak temperatures.

Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation

tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com.

Figure 9. 56-Pin (8 × 8 mm) QFN (Punched)

Important Note

■ For information on the preferred dimensions for mounting QFN packages, see the following application note, Application Notes for

Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com.

■ Pinned vias for thermal conduction are not required for the low power PSoC device.

Thermal Impedances Solder Reflow Specifications

Tabl e 2 9 shows the solder reflow temperature limits that must not

be exceeded.

SOLDERABLE

EXPOSED

PAD

001-12921 *B

Table 28. Thermal Impedance per Package

Package Typical 

[22]

Typical 

56-pin QFN

[23]

19 C/W 1.7 C/W

Table 29. Solder Reflow Specifications

Package

Maximum Peak

Temperature (T

)

Maximum Time

above T

– 5 °C

56-pin QFN 260 C 30 seconds

Notes

22. T

= T

+ Power × 

JA.

23. To achieve the thermal impedance specified for the QFN package, refer to the application notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF)

Packages available at http://www.amkor.com.

1 2 ... 30 31 32 33 34 35 36 37 38 39 40 ... 49 50

Comentarios a estos manuales

Sin comentarios

Cypress Semiconductor CY8C24894 Especificaciones Pagina 35

Comentarios a estos manuales

Relacionado con productos y manuales para No Cypress Semiconductor CY8C24894