Cypress Semiconductor CY8C24894 Especificaciones descargar pdf (Pagina 34)

CY8C24894

Document Number: 001-53754 Rev. *F Page 34 of 50

AC I

C Specifications

Tab le 27 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40

°C  T

 85 °C, or 3.0 V to 3.6 V and –40 °C  T

 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are

for design guidance only.

Figure 8. Definition for Timing for Fast/Standard Mode on the I

C Bus

Table 27. AC Characteristics of the I

C SDA and SCL Pins for V

Symbol Description

Standard Mode Fast Mode

Units Notes

Min Max Min Max

SCLI2C

SCL clock frequency 0 100

[20]

0 400

[20]

kHz

HDSTAI2C

Hold time (repeated) START condition. After

this period, the first clock pulse is generated.

4.0 –0.6– s

LOWI2C

LOW period of the SCL clock 4.7 –1.3– s

HIGHI2C

HIGH period of the SCL clock 4.0 –0.6– s

SUSTAI2C

Setup time for a repeated START condition 4.7 –0.6– s

HDDATI2C

Data hold time 0 –0– s

SUDATI2C

Data setup time 250 – 100

[21]

–ns

SUSTOI2C

Setup time for STOP condition 4.0 –0.6– s

BUFI2C

Bus free time between a stop and start

condition

4.7 –1.3– s

SPI2C

Pulse width of spikes are suppressed by the

input filter.

– – 0 50 ns

I2C_SDA

I2C_SCL

BUFI2C

SPI2C

SUSTOI2C

SUSTAI2C

LOWI2C

HIGHI2C

HDDATI2C

HDSTAI2C

SUDATI2C

START Condition Repeated START Condition

STOP Condition

Notes

20. F

SCLI2C

is derived from SysClk of the PSoC. This specification assumes that SysClk is operating at 24 MHz, nominal. If SysClk is at a lower frequency, then the F

SCLI2C

specification adjusts accordingly.

21. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement t

SUDATI2C

 250 ns must then be met. This is automatically the

case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to

the SDA line t

rmax

+ t

SUDATI2C

= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.

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