Cypress Semiconductor CY8C24894 Especificaciones Pagina 27

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CY8C24894
Document Number: 001-53754 Rev. *F Page 27 of 50
AC Electrical Characteristics
AC Chip-Level Specifications
Tab le 17 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40
°C T
A
85 °C, or 3.0 V to 3.6 V and –40 °C T
A
85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are
for design guidance only.
Notes
13. Accuracy derived from IMO with appropriate trim for V
DD
range.
14. See the individual user module datasheets for information on maximum frequencies for user modules.
15. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
Table 17. AC Chip-Level Specifications
Symbol Description Min Typ Max Units Notes
F
IMO245V
IMO frequency for 24 MHz (5 V
nominal)
23.04
[13]
24 24.96
[13]
MHz Trimmed for 5 V operation using
factory trim values.
F
IMO243V
IMO frequency for 24 MHz (3.3 V
nominal)
22.08
[13]
24 25.92
[13]
MHz Trimmed for 3.3 V operation using
factory trim values.
F
CPU1
CPU frequency (5 V nominal) 0.090
[13]
24 24.96
[13]
MHz SLIMO mode = 0.
F
CPU2
CPU frequency (3.3 V nominal) 0.086
[13]
12 12.96
[13]
MHz SLIMO mode = 0.
F
BLK5
Digital PSoC block frequency (5 V
nominal)
0 48 49.92
[13,14]
MHz Refer to the AC Digital Block
Specifications.
F
BLK3
Digital PSoC block frequency (3.3 V
nominal)
0 24 25.92
[13,14]
MHz Refer to the AC Digital Block
Specifications.
F
32K1
ILO frequency 15 32 64 kHz This specification applies when
the ILO has been trimmed.
F
32KU
ILO untrimmed frequency 5 100 kHz After a reset and before the M8C
processor starts to execute, the
ILO is not trimmed.
t
XRST
External reset pulse width 10 µs
DC24M 24 MHz duty cycle 40 50 60 %
DC
ILO
ILO duty cycle 20 50 80 %
Step24M 24 MHz trim step size 50 kHz
Fout48M 48 MHz output frequency 46.08
[13]
48 49.92
[13]
MHz 4.75 V V
DD
5.25 V
F
MAX
Maximum frequency of signal on row
input or row output.
12.96
[13]
MHz
SR
POWERUP
Power supply slew rate 250 V/ms V
DD
slew rate during power-up.
t
POWERUP
Time between end of POR state and
CPU code execution
16 100 ms Power-up from 0 V.
t
JIT_IMO
[15]
24 MHz IMO cycle-to-cycle jitter (RMS) 200 1200 ps
24 MHz IMO long term N cycle-to-cycle
jitter (RMS)
900 6000 ps N = 32
24 MHz IMO period jitter (RMS) 200 900 ps
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